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Remove 'clkpart' entry in CHANGELOG

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Eddie Hung 2019-12-12 15:02:46 -08:00
parent bea15b537b
commit fce6bad6ae
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@ -53,7 +53,6 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "check -mapped" - Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb, - Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff) always_latch and always_ff)
- Added "clkpart" pass
Yosys 0.8 .. Yosys 0.9 Yosys 0.8 .. Yosys 0.9
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