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write_verilog: add a missing newline.

This commit is contained in:
whitequark 2018-12-13 04:36:02 +00:00
parent 435776120a
commit fccaa25ec1
1 changed files with 1 additions and 1 deletions
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2
backends/verilog/verilog_backend.cc
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@ -1419,7 +1419,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n" log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
"can't always be mapped directly to Verilog always blocks. Unintended\n" "can't always be mapped directly to Verilog always blocks. Unintended\n"
"changes in simulation behavior are possible! Use \"proc\" to convert\n" "changes in simulation behavior are possible! Use \"proc\" to convert\n"
"processes to logic networks and registers.", log_id(module)); "processes to logic networks and registers.\n", log_id(module));
f << stringf("\n"); f << stringf("\n");
for (auto it = module->processes.begin(); it != module->processes.end(); ++it) for (auto it = module->processes.begin(); it != module->processes.end(); ++it)