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Simplified $fa undef model

This commit is contained in:
Clifford Wolf 2014-09-08 16:59:39 +02:00
parent 6dc07eb1f2
commit fcb46138ce
3 changed files with 6 additions and 15 deletions
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4
kernel/consteval.h
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@ -214,6 +214,10 @@ struct ConstEval
RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width); RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);
RTLIL::Const val_x = const_or(t2, t3, false, false, width); RTLIL::Const val_x = const_or(t2, t3, false, false, width);
for (int i = 0; i < SIZE(val_y); i++)
if (val_y.bits[i] == RTLIL::Sx)
val_x.bits[i] = RTLIL::Sx;
set(sig_y, val_y); set(sig_y, val_y);
set(sig_x, val_x); set(sig_x, val_x);
} }

15
kernel/satgen.h
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@ -991,20 +991,7 @@ struct SatGen
std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep);
ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
ez->assume(ez->vec_eq(undef_x, undef_y));
std::vector<int> undef_t1 = ez->vec_or(undef_a, undef_b);
std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a));
std::vector<int> b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b));
std::vector<int> undef_t2 = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0)));
std::vector<int> c0 = ez->vec_and(ez->vec_not(c), ez->vec_not(undef_c));
std::vector<int> t10 = ez->vec_and(ez->vec_not(t1), ez->vec_not(undef_t1));
std::vector<int> undef_t3 = ez->vec_and(ez->vec_or(undef_c, undef_t1), ez->vec_not(ez->vec_or(c0, t10)));
std::vector<int> t21 = ez->vec_and(t2, ez->vec_not(undef_t2));
std::vector<int> t31 = ez->vec_and(t3, ez->vec_not(undef_t3));
ez->assume(ez->vec_eq(undef_x, ez->vec_and(ez->vec_or(undef_t2, undef_t3), ez->vec_not(ez->vec_or(t21, t31)))));
undefGating(y, yy, undef_y); undefGating(y, yy, undef_y);
undefGating(x, xx, undef_x); undefGating(x, xx, undef_x);

2
techlibs/common/simlib.v
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@ -453,7 +453,7 @@ output [WIDTH-1:0] X, Y;
wire [WIDTH-1:0] t1, t2, t3; wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1; assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
assign Y = t1 ^ C, X = t2 | t3; assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);
endmodule endmodule