mirror of https://github.com/YosysHQ/yosys.git
Add ConstEval defaultval feature
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@ -36,8 +36,9 @@ struct ConstEval
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SigSet<RTLIL::Cell*> sig2driver;
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SigSet<RTLIL::Cell*> sig2driver;
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std::set<RTLIL::Cell*> busy;
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std::set<RTLIL::Cell*> busy;
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std::vector<SigMap> stack;
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std::vector<SigMap> stack;
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RTLIL::State defaultval;
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ConstEval(RTLIL::Module *module) : module(module), assign_map(module)
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ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)
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{
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{
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CellTypes ct;
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CellTypes ct;
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ct.setup_internals();
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ct.setup_internals();
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@ -365,6 +366,12 @@ struct ConstEval
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if (sig.is_fully_const())
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if (sig.is_fully_const())
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return true;
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return true;
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if (defaultval != RTLIL::State::Sm) {
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for (auto &bit : sig)
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if (bit.wire) bit = defaultval;
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return true;
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}
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for (auto &c : sig.chunks())
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for (auto &c : sig.chunks())
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if (c.wire != NULL)
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if (c.wire != NULL)
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undef.append(c);
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undef.append(c);
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