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Check DREG attribute 

The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
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Oliver Keszöcze 2023-02-17 17:54:41 +01:00 committed by GitHub
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commit fc56978703
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techlibs/xilinx/cells_sim.v
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@ -3614,7 +3614,7 @@ module DSP48E1 (
if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end
else always @* Cr <= C; else always @* Cr <= C;
if (CREG == 1) initial Dr = 25'b0; if (DREG == 1) initial Dr = 25'b0;
if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
else always @* Dr <= D; else always @* Dr <= D;