riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Check DREG attribute 

The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
This commit is contained in:
Oliver Keszöcze 2023-02-17 17:54:41 +01:00 committed by GitHub
parent 1cfedc90ce
commit fc56978703
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/xilinx/cells_sim.v
View File

@ -3614,7 +3614,7 @@ module DSP48E1 (
if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end
else always @* Cr <= C;
if (CREG == 1) initial Dr = 25'b0;
if (DREG == 1) initial Dr = 25'b0;
if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
else always @* Dr <= D;