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Merge pull request #3511 from YosysHQ/improve_edif 

verific: enable import all cells
This commit is contained in:
Miodrag Milanović 2022-10-14 17:53:56 +02:00 committed by GitHub
parent 2e837956dc 48628fbf5a
commit fc53a0a5c2
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 31 additions and 1 deletions
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32
frontends/verific/verific.cc
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@ -2533,6 +2533,10 @@ struct VerificPass : public Pass {
log(" -fullinit\n");
log(" Keep all register initializations, even those for non-FF registers.\n");
log("\n");
log(" -cells\n");
log(" Import all cell definitions from Verific loaded libraries even if they are\n");
log(" unused in design. Useful with \"-edif\" option.\n");
log("\n");
log(" -chparam name value \n");
log(" Elaborate the specified top modules (all modules when -all given) using\n");
log(" this parameter value. Modules on which this parameter does not exist will\n");
@ -3052,7 +3056,7 @@ struct VerificPass : public Pass {
bool mode_all = false, mode_gates = false, mode_keep = false;
bool mode_nosva = false, mode_names = false, mode_verific = false;
bool mode_autocover = false, mode_fullinit = false;
bool flatten = false, extnets = false;
bool flatten = false, extnets = false, mode_cells = false;
string dumpfile;
string ppfile;
Map parameters(STRING_HASH);
@ -3098,6 +3102,10 @@ struct VerificPass : public Pass {
mode_fullinit = true;
continue;
}
if (args[argidx] == "-cells") {
mode_cells = true;
continue;
}
if (args[argidx] == "-chparam" && argidx+2 < GetSize(args)) {
const std::string &key = args[++argidx];
const std::string &value = args[++argidx];
@ -3218,6 +3226,28 @@ struct VerificPass : public Pass {
}
delete netlists;
}
if (mode_cells) {
log("Importing all cells.\n");
Libset *gls = Libset::Global() ;
MapIter it ;
Library *l ;
FOREACH_LIBRARY_OF_LIBSET(gls,it,l) {
MapIter mi ;
Verific::Cell *c ;
FOREACH_CELL_OF_LIBRARY(l,mi,c) {
if (!mode_verific && (l == Library::Primitives() || l == Library::Operators())) continue;
MapIter ni ;
if (c->NumOfNetlists() == 1) {
c->GetFirstNetlist()->SetName("");
}
Netlist *nl;
FOREACH_NETLIST_OF_CELL(c, ni, nl) {
if (nl)
nl_todo.emplace(nl->CellBaseName(), nl);
}
}
}
}
if (!verific_error_msg.empty())
goto check_error;