mirror of https://github.com/YosysHQ/yosys.git
wreduce for $sub
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@ -365,6 +365,29 @@ struct WreduceWorker
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}
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}
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}
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}
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if (cell->type.in("$add", "$sub")) {
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SigSpec A = cell->getPort("\\A");
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SigSpec B = cell->getPort("\\B");
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bool sub = cell->type == "$sub";
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int i;
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for (i = 0; i < GetSize(sig); i++) {
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if (B[i] != S0 && (sub || A[i] != S0))
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break;
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if (B[i] == S0)
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module->connect(sig[i], A[i]);
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else if (A[i] == S0)
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module->connect(sig[i], B[i]);
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else log_abort();
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}
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if (i > 0) {
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cell->setPort("\\A", A.extract(i, -1));
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cell->setPort("\\B", B.extract(i, -1));
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sig.remove(0, i);
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bits_removed += i;
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}
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}
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if (GetSize(sig) == 0) {
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if (GetSize(sig) == 0) {
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log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
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log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
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module->remove(cell);
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module->remove(cell);
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