mirror of https://github.com/YosysHQ/yosys.git
equiv_make: Add -make_assert option
This adds a -make_assert flag to equiv_make. When used, the pass generates $eqx and $assert cells to encode equivalence instead of $equiv.
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@ -33,6 +33,7 @@ struct EquivMakeWorker
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bool inames;
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vector<string> blacklists;
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vector<string> encfiles;
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bool make_assert;
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pool<IdString> blacklist_names;
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dict<IdString, dict<Const, Const>> encdata;
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@ -143,6 +144,12 @@ struct EquivMakeWorker
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delete gate_clone;
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}
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void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig)
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{
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auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig);
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equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1);
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}
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void find_same_wires()
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{
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SigMap assign_map(equiv_mod);
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@ -240,15 +247,24 @@ struct EquivMakeWorker
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if (gold_wire->port_output || gate_wire->port_output)
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{
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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wire->port_output = true;
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gold_wire->port_input = false;
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gate_wire->port_input = false;
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gold_wire->port_output = false;
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gate_wire->port_output = false;
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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wire->port_output = true;
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if (make_assert)
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{
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add_eq_assertion(gold_wire, gate_wire);
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equiv_mod->connect(wire, gold_wire);
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}
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else
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{
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for (int i = 0; i < wire->width; i++)
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equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
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}
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rd_signal_map.add(assign_map(gold_wire), wire);
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rd_signal_map.add(assign_map(gate_wire), wire);
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@ -265,6 +281,10 @@ struct EquivMakeWorker
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}
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else
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{
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if (make_assert)
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add_eq_assertion(gold_wire, gate_wire);
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else {
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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SigSpec rdmap_gold, rdmap_gate, rdmap_equiv;
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@ -287,6 +307,7 @@ struct EquivMakeWorker
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rd_signal_map.add(rdmap_gate, rdmap_equiv);
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}
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}
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}
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init_bit2driven();
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@ -353,12 +374,20 @@ struct EquivMakeWorker
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continue;
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}
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if (make_assert)
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{
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if (gold_sig != gate_sig)
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add_eq_assertion(gold_sig, gate_sig);
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}
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else
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{
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for (int i = 0; i < GetSize(gold_sig); i++)
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if (gold_sig[i] != gate_sig[i]) {
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Wire *w = equiv_mod->addWire(NEW_ID);
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equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
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gold_sig[i] = w;
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}
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}
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gold_cell->setPort(gold_conn.first, gold_sig);
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}
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@ -486,6 +515,10 @@ struct EquivMakePass : public Pass {
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log(" Match FSM encodings using the description from the file.\n");
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log(" See 'help fsm_recode' for details.\n");
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log("\n");
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log(" -make_assert\n");
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log(" Check equivalence with $assert cells instead of $equiv.\n");
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log(" $eqx (===) is used to compare signals.");
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log("\n");
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log("Note: The circuit created by this command is not a miter (with something like\n");
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log("a trigger output), but instead uses $equiv cells to encode the equivalence\n");
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log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
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@ -496,6 +529,7 @@ struct EquivMakePass : public Pass {
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EquivMakeWorker worker;
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worker.ct.setup(design);
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worker.inames = false;
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worker.make_assert = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -512,6 +546,10 @@ struct EquivMakePass : public Pass {
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worker.encfiles.push_back(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-make_assert") {
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worker.make_assert = true;
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continue;
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}
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break;
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}
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@ -0,0 +1,32 @@
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read_verilog <<EOT
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module gold(
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input wire [7:0] a,
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input wire [7:0] b,
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output wire [7:0] c
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);
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wire [7:0] b_neg;
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assign b_neg = -b;
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assign c = a + b_neg;
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endmodule
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module gate(
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input wire [7:0] a,
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input wire [7:0] b,
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output wire [7:0] c
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);
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wire [7:0] b_neg;
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assign b_neg = ~b + 1;
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assign c = a + b_neg;
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endmodule
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EOT
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equiv_make -make_assert gold gate miter
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select -assert-count 0 t:$equiv
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select -assert-count 2 t:$assert
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prep -top miter
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sat -prove-asserts -verify
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