mirror of https://github.com/YosysHQ/yosys.git
Allow module name to be determined by argument too
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f1befe1b44
commit
fb8ad440a3
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@ -30,11 +30,11 @@ YOSYS_NAMESPACE_BEGIN
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#define log_debug log
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name)
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
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: design(design), f(f), clk_name(clk_name)
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{
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module = new RTLIL::Module;
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module->name = RTLIL::escape_id("aig"); // TODO: Name?
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module->name = module_name;
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if (design->module(module->name))
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log_error("Duplicate definition of module %s!\n", log_id(module->name));
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}
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@ -162,11 +162,10 @@ void AigerReader::parse_aiger_ascii()
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// Parse latches
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0) {
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RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
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clk_wire = module->wire(clk_id);
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clk_wire = module->wire(clk_name);
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log_assert(!clk_wire);
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log_debug("Creating %s\n", clk_id.c_str());
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clk_wire = module->addWire(clk_id);
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log_debug("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(clk_name);
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clk_wire->port_input = true;
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}
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for (unsigned i = 0; i < L; ++i, ++line_count) {
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@ -270,11 +269,10 @@ void AigerReader::parse_aiger_binary()
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// Parse latches
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0) {
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RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
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clk_wire = module->wire(clk_id);
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clk_wire = module->wire(clk_name);
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log_assert(!clk_wire);
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log_debug("Creating %s\n", clk_id.c_str());
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clk_wire = module->addWire(clk_id);
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log_debug("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(clk_name);
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clk_wire->port_input = true;
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}
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l1 = (I+1) * 2;
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@ -364,21 +362,53 @@ struct AigerFrontend : public Frontend {
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log("\n");
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log(" read_aiger [options] [filename]\n");
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log("\n");
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log("Load modules from an AIGER file into the current design.\n");
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log("Load module from an AIGER file into the current design.\n");
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log("\n");
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log(" -clk_name <wire_name>\n");
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log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
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log(" this name (default: clk)\n");
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log("\n");
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log(" -module_name <module_name>\n");
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log(" Name of module to be created (default: <filename>)"
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#ifdef _WIN32
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"top" // FIXME
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#else
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"<filename>"
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#endif
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")\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing AIGER frontend.\n");
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RTLIL::IdString clk_name = "\\clk";
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RTLIL::IdString module_name;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-clk_name" && argidx+1 < args.size()) {
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clk_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (arg == "-module_name" && argidx+1 < args.size()) {
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module_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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AigerReader reader(design, *f);
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if (module_name.empty()) {
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#ifdef _WIN32
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module_name = "top"; // FIXME: basename equivalent on Win32?
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#else
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module_name = RTLIL::escape_id(basename(filename.c_str()));
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#endif
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}
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AigerReader reader(design, *f, module_name, clk_name);
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reader.parse_aiger();
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}
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} AigerFrontend;
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@ -28,7 +28,7 @@ struct AigerReader
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{
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RTLIL::Design *design;
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std::istream &f;
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std::string clk_name;
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RTLIL::IdString clk_name;
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RTLIL::Module *module;
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unsigned M, I, L, O, A;
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@ -39,7 +39,7 @@ struct AigerReader
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std::vector<RTLIL::Wire*> latches;
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std::vector<RTLIL::Wire*> outputs;
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AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
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AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name);
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void parse_aiger();
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void parse_aiger_ascii();
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void parse_aiger_binary();
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