mirror of https://github.com/YosysHQ/yosys.git
Add support for various ff/latch cells simulation
This commit is contained in:
Miodrag Milanovic
parent
1586000048
commit
fb22d7cdc4
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@ -109,7 +109,6 @@ void FstData::extractVarNames()
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}
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if (clean_name[0]=='\\')
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clean_name = clean_name.substr(1);
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//log("adding %s.%s\n",var.scope.c_str(), clean_name.c_str());
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name_to_handle[var.scope+"."+clean_name] = h->u.var.handle;
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break;
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@ -118,48 +117,6 @@ void FstData::extractVarNames()
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}
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}
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static void reconstruct_edges_varlen(void *user_data, uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t plen)
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{
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FstData *ptr = (FstData*)user_data;
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ptr->reconstruct_edges_callback(pnt_time, pnt_facidx, pnt_value, plen);
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}
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static void reconstruct_edges(void *user_data, uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value)
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{
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FstData *ptr = (FstData*)user_data;
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uint32_t plen = (pnt_value) ? strlen((const char *)pnt_value) : 0;
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ptr->reconstruct_edges_callback(pnt_time, pnt_facidx, pnt_value, plen);
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}
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void FstData::reconstruct_edges_callback(uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t /* plen */)
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{
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std::string val = std::string((const char *)pnt_value);
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std::string prev = last_data[pnt_facidx];
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if (pnt_time>=start_time) {
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if (prev!="1" && val=="1")
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edges.push_back(pnt_time);
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if (prev!="0" && val=="0")
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edges.push_back(pnt_time);
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}
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last_data[pnt_facidx] = val;
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}
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std::vector<uint64_t> FstData::getAllEdges(std::vector<fstHandle> &signal, uint64_t start, uint64_t end)
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{
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start_time = start;
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end_time = end;
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last_data.clear();
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for(auto &s : signal) {
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last_data[s] = "x";
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}
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edges.clear();
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fstReaderSetLimitTimeRange(ctx, start_time, end_time);
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fstReaderClrFacProcessMaskAll(ctx);
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for(const auto sig : signal)
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fstReaderSetFacProcessMask(ctx,sig);
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fstReaderIterBlocks2(ctx, reconstruct_edges, reconstruct_edges_varlen, this, nullptr);
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return edges;
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}
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static void reconstruct_clb_varlen_attimes(void *user_data, uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t plen)
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{
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@ -176,77 +133,65 @@ static void reconstruct_clb_attimes(void *user_data, uint64_t pnt_time, fstHandl
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void FstData::reconstruct_callback_attimes(uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t /* plen */)
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{
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if (sample_times_ndx >= sample_times.size()) return;
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uint64_t time = sample_times[sample_times_ndx];
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if (pnt_time > end_time) return;
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// if we are past the timestamp
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if (pnt_time > time) {
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for (auto const& c : last_data)
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{
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handle_to_data[c.first].push_back(std::make_pair(time,c.second));
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size_t index = handle_to_data[c.first].size() - 1;
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time_to_index[c.first][time] = index;
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bool is_clock = false;
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if (!all_samples) {
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for(auto &s : clk_signals) {
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if (s==pnt_facidx) {
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is_clock=true;
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break;
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}
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}
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}
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if (pnt_time > past_time) {
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past_data = last_data;
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past_time = pnt_time;
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}
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if (pnt_time > last_time) {
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if (all_samples) {
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callback(last_time);
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last_time = pnt_time;
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} else {
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if (is_clock) {
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std::string val = std::string((const char *)pnt_value);
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std::string prev = past_data[pnt_facidx];
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if ((prev!="1" && val=="1") || (prev!="0" && val=="0")) {
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callback(last_time);
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last_time = pnt_time;
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}
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}
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}
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sample_times_ndx++;
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}
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// always update last_data
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last_data[pnt_facidx] = std::string((const char *)pnt_value);
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}
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void FstData::reconstructAtTimes(std::vector<fstHandle> &signal, std::vector<uint64_t> time)
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void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t start, uint64_t end, CallbackFunction cb)
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{
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handle_to_data.clear();
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time_to_index.clear();
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clk_signals = signal;
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callback = cb;
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start_time = start;
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end_time = end;
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last_data.clear();
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sample_times_ndx = 0;
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sample_times = time;
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fstReaderSetUnlimitedTimeRange(ctx);
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fstReaderClrFacProcessMaskAll(ctx);
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for(const auto sig : signal)
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fstReaderSetFacProcessMask(ctx,sig);
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fstReaderIterBlocks2(ctx, reconstruct_clb_attimes, reconstruct_clb_varlen_attimes, this, nullptr);
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if (time_to_index[signal.back()].count(time.back())==0) {
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for (auto const& c : last_data)
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{
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handle_to_data[c.first].push_back(std::make_pair(time.back(),c.second));
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size_t index = handle_to_data[c.first].size() - 1;
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time_to_index[c.first][time.back()] = index;
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}
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}
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}
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void FstData::reconstructAllAtTimes(std::vector<uint64_t> time)
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{
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handle_to_data.clear();
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time_to_index.clear();
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last_data.clear();
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sample_times_ndx = 0;
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sample_times = time;
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last_time = start_time;
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past_data.clear();
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past_time = start_time;
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all_samples = clk_signals.empty();
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fstReaderSetUnlimitedTimeRange(ctx);
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fstReaderSetFacProcessMaskAll(ctx);
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fstReaderIterBlocks2(ctx, reconstruct_clb_attimes, reconstruct_clb_varlen_attimes, this, nullptr);
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if (time_to_index[1].count(time.back())==0) {
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for (auto const& c : last_data)
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{
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handle_to_data[c.first].push_back(std::make_pair(time.back(),c.second));
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size_t index = handle_to_data[c.first].size() - 1;
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time_to_index[c.first][time.back()] = index;
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}
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}
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callback(last_time);
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if (last_time!=end_time)
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callback(end_time);
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}
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std::string FstData::valueAt(fstHandle signal, uint64_t time)
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std::string FstData::valueOf(fstHandle signal)
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{
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if (handle_to_data.find(signal) == handle_to_data.end())
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if (past_data.find(signal) == past_data.end())
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log_error("Signal id %d not found\n", (int)signal);
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auto &data = handle_to_data[signal];
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if (time_to_index[signal].count(time)!=0) {
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size_t index = time_to_index[signal][time];
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return data.at(index).second;
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} else {
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log_error("No data for signal %d at time %d\n", (int)signal, (int)time);
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}
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return past_data[signal];
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}
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@ -25,6 +25,9 @@
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YOSYS_NAMESPACE_BEGIN
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typedef std::function<void(uint64_t)> CallbackFunction;
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struct fst_end_of_data_exception { };
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struct FstVar
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{
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fstHandle id;
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@ -45,14 +48,10 @@ class FstData
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std::vector<FstVar>& getVars() { return vars; };
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void reconstruct_edges_callback(uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t plen);
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std::vector<uint64_t> getAllEdges(std::vector<fstHandle> &signal, uint64_t start_time, uint64_t end_time);
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void reconstruct_callback_attimes(uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t plen);
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void reconstructAtTimes(std::vector<fstHandle> &signal,std::vector<uint64_t> time);
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void reconstructAllAtTimes(std::vector<uint64_t> time);
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void reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t start_time, uint64_t end_time, CallbackFunction cb);
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std::string valueAt(fstHandle signal, uint64_t time);
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std::string valueOf(fstHandle signal);
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fstHandle getHandle(std::string name);
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double getTimescale() { return timescale; }
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const char *getTimescaleString() { return timescale_str.c_str(); }
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@ -64,16 +63,17 @@ private:
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std::vector<FstVar> vars;
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std::map<fstHandle, FstVar> handle_to_var;
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std::map<std::string, fstHandle> name_to_handle;
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std::map<fstHandle, std::vector<std::pair<uint64_t, std::string>>> handle_to_data;
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std::map<fstHandle, std::string> last_data;
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std::map<fstHandle, std::map<uint64_t, size_t>> time_to_index;
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std::vector<uint64_t> sample_times;
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size_t sample_times_ndx;
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uint64_t last_time;
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std::map<fstHandle, std::string> past_data;
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uint64_t past_time;
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double timescale;
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std::string timescale_str;
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uint64_t start_time;
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uint64_t end_time;
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std::vector<uint64_t> edges;
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CallbackFunction callback;
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std::vector<fstHandle> clk_signals;
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bool all_samples;
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};
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YOSYS_NAMESPACE_END
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@ -22,6 +22,7 @@
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#include "kernel/celltypes.h"
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#include "kernel/mem.h"
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#include "kernel/fstdata.h"
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#include "kernel/ff.h"
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#include <ctime>
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@ -76,6 +77,7 @@ struct SimShared
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double stop_time = -1;
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SimulationMode sim_mode = SimulationMode::sim;
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bool cycles_set = false;
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const pool<IdString> ff_types = RTLIL::builtin_ff_cell_types();
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};
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void zinit(State &v)
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@ -113,8 +115,13 @@ struct SimInstance
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struct ff_state_t
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{
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State past_clock;
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Const past_d;
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Const past_ad;
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SigSpec past_clk;
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SigSpec past_ce;
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SigSpec past_srst;
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FfData data;
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};
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struct mem_state_t
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@ -209,10 +216,15 @@ struct SimInstance
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}
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}
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if (cell->type.in(ID($dff))) {
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if (shared->ff_types.count(cell->type)) {
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FfData ff_data(nullptr, cell);
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ff_state_t ff;
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ff.past_clock = State::Sx;
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ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int());
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ff.past_d = Const(State::Sx, ff_data.width);
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ff.past_ad = Const(State::Sx, ff_data.width);
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ff.past_clk = State::Sx;
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ff.past_ce = State::Sx;
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ff.past_srst = State::Sx;
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ff.data = ff_data;
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ff_database[cell] = ff;
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}
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@ -229,11 +241,10 @@ struct SimInstance
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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zinit(ff.past_d);
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SigSpec qsig = cell->getPort(ID::Q);
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SigSpec qsig = it.second.data.sig_q;
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Const qdata = get_state(qsig);
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zinit(qdata);
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set_state(qsig, qdata);
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@ -466,20 +477,138 @@ struct SimInstance
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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FfData ff_data = ff.data;
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if (cell->type.in(ID($dff)))
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{
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bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool();
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State current_clock = get_state(cell->getPort(ID::CLK))[0];
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if (ff_data.has_clk) {
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// flip-flops
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State current_clk = get_state(ff_data.sig_clk)[0];
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if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
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(ff.past_clock == State::S0 || current_clock != State::S0))
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continue;
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// handle set/reset
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if (ff.data.has_sr) {
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Const current_q = get_state(ff.data.sig_q);
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Const current_clr = get_state(ff.data.sig_clr);
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Const current_set = get_state(ff.data.sig_set);
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if (set_state(cell->getPort(ID::Q), ff.past_d))
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did_something = true;
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for(int i=0;i<ff.past_d.size();i++) {
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if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
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current_q[i] = State::S0;
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}
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else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
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current_q[i] = State::S1;
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} else {
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// all below is in sync with clk
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if (ff_data.pol_clk ? (ff.past_clk == State::S1 || current_clk != State::S1) :
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(ff.past_clk == State::S0 || current_clk != State::S0))
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continue;
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if (ff_data.has_ce) {
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if (ff.past_ce == (ff_data.pol_ce ? State::S1 : State::S0))
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current_q[i] = ff.past_d[i];
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} else {
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current_q[i] = ff.past_d[i];
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}
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}
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}
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if (set_state(ff_data.sig_q, current_q))
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did_something = true;
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} else {
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// async reset
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if (ff_data.has_arst) {
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State current_arst = get_state(ff_data.sig_arst)[0];
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if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_arst))
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did_something = true;
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continue;
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}
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}
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// async load
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if (ff_data.has_aload) {
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff.past_ad))
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did_something = true;
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continue;
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}
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}
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// all below is in sync with clk
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if (ff_data.pol_clk ? (ff.past_clk == State::S1 || current_clk != State::S1) :
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(ff.past_clk == State::S0 || current_clk != State::S0))
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continue;
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// chip enable priority over reset
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if (ff_data.ce_over_srst && ff_data.has_ce) {
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if (ff.past_ce != (ff_data.pol_ce ? State::S1 : State::S0))
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continue;
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}
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// handle sync reset
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if (ff_data.has_srst) {
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if (ff.past_srst == (ff_data.pol_srst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_srst))
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did_something = true;
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continue;
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}
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}
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// reset had priority over chip enable
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if (!ff_data.ce_over_srst && ff_data.has_ce) {
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if (ff.past_ce != (ff_data.pol_ce ? State::S1 : State::S0))
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continue;
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}
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if (set_state(ff_data.sig_q, ff.past_d))
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did_something = true;
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}
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} else {
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// handle set/reset
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if (ff.data.has_sr) {
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Const current_q = get_state(ff.data.sig_q);
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Const current_clr = get_state(ff.data.sig_clr);
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Const current_set = get_state(ff.data.sig_set);
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for(int i=0;i<current_q.size();i++) {
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if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
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current_q[i] = State::S0;
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}
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else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
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current_q[i] = State::S1;
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} else {
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if (ff_data.has_aload) {
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Const current_ad = get_state(ff.data.sig_ad);
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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current_q[i] = current_ad[i];
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}
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}
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}
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}
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if (set_state(ff_data.sig_q, current_q))
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did_something = true;
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}
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// async load is true for all latches
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||||
else if (ff_data.has_aload) {
|
||||
// async reset
|
||||
if (ff_data.has_arst) {
|
||||
State current_arst = get_state(ff_data.sig_arst)[0];
|
||||
if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
|
||||
if (set_state(ff_data.sig_q, ff_data.val_arst))
|
||||
did_something = true;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
State current_aload = get_state(ff_data.sig_aload)[0];
|
||||
if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
|
||||
if (set_state(ff_data.sig_q, get_state(ff.data.sig_ad)))
|
||||
did_something = true;
|
||||
}
|
||||
} else if (ff_data.has_gclk) {
|
||||
// $ff
|
||||
if (set_state(ff_data.sig_q, ff.past_d))
|
||||
did_something = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -538,13 +667,22 @@ struct SimInstance
|
|||
{
|
||||
for (auto &it : ff_database)
|
||||
{
|
||||
Cell *cell = it.first;
|
||||
ff_state_t &ff = it.second;
|
||||
|
||||
if (cell->type.in(ID($dff))) {
|
||||
ff.past_clock = get_state(cell->getPort(ID::CLK))[0];
|
||||
ff.past_d = get_state(cell->getPort(ID::D));
|
||||
}
|
||||
if (ff.data.has_aload)
|
||||
ff.past_ad = get_state(ff.data.sig_ad);
|
||||
|
||||
if (ff.data.has_clk || ff.data.has_gclk)
|
||||
ff.past_d = get_state(ff.data.sig_d);
|
||||
|
||||
if (ff.data.has_clk)
|
||||
ff.past_clk = get_state(ff.data.sig_clk)[0];
|
||||
|
||||
if (ff.data.has_ce)
|
||||
ff.past_ce = get_state(ff.data.sig_ce)[0];
|
||||
|
||||
if (ff.data.has_srst)
|
||||
ff.past_srst = get_state(ff.data.sig_srst)[0];
|
||||
}
|
||||
|
||||
for (auto &it : mem_database)
|
||||
|
|
@ -595,8 +733,7 @@ struct SimInstance
|
|||
|
||||
for (auto &it : ff_database)
|
||||
{
|
||||
Cell *cell = it.first;
|
||||
SigSpec sig_q = cell->getPort(ID::Q);
|
||||
SigSpec sig_q = it.second.data.sig_q;
|
||||
Const initval = get_state(sig_q);
|
||||
|
||||
for (int i = 0; i < GetSize(sig_q); i++)
|
||||
|
|
@ -722,34 +859,32 @@ struct SimInstance
|
|||
child.second->write_fst_step(f);
|
||||
}
|
||||
|
||||
void setInitState(uint64_t time)
|
||||
void setInitState()
|
||||
{
|
||||
for (auto &it : ff_database)
|
||||
{
|
||||
Cell *cell = it.first;
|
||||
|
||||
SigSpec qsig = cell->getPort(ID::Q);
|
||||
SigSpec qsig = it.second.data.sig_q;
|
||||
if (qsig.is_wire()) {
|
||||
IdString name = qsig.as_wire()->name;
|
||||
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
|
||||
if (id==0 && name.isPublic())
|
||||
log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
|
||||
if (id!=0) {
|
||||
Const fst_val = Const::from_string(shared->fst->valueAt(id, time));
|
||||
Const fst_val = Const::from_string(shared->fst->valueOf(id));
|
||||
set_state(qsig, fst_val);
|
||||
}
|
||||
}
|
||||
}
|
||||
for (auto child : children)
|
||||
child.second->setInitState(time);
|
||||
child.second->setInitState();
|
||||
}
|
||||
|
||||
bool checkSignals(uint64_t time)
|
||||
bool checkSignals()
|
||||
{
|
||||
bool retVal = false;
|
||||
for(auto &item : fst_handles) {
|
||||
if (item.second==0) continue; // Ignore signals not found
|
||||
Const fst_val = Const::from_string(shared->fst->valueAt(item.second, time));
|
||||
Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
|
||||
Const sim_val = get_state(item.first);
|
||||
if (sim_val.size()!=fst_val.size())
|
||||
log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
|
||||
|
|
@ -779,7 +914,7 @@ struct SimInstance
|
|||
}
|
||||
}
|
||||
for (auto child : children)
|
||||
retVal |= child.second->checkSignals(time);
|
||||
retVal |= child.second->checkSignals();
|
||||
return retVal;
|
||||
}
|
||||
};
|
||||
|
|
@ -998,8 +1133,6 @@ struct SimWorker : SimShared
|
|||
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
|
||||
fst_clock.push_back(id);
|
||||
}
|
||||
if (fst_clock.size()==0)
|
||||
log_error("No clock signals defined for input file\n");
|
||||
|
||||
SigMap sigmap(topmod);
|
||||
std::map<Wire*,fstHandle> inputs;
|
||||
|
|
@ -1044,37 +1177,48 @@ struct SimWorker : SimShared
|
|||
if (stopCount<startCount) {
|
||||
log_error("Stop time is before start time\n");
|
||||
}
|
||||
auto samples = fst->getAllEdges(fst_clock, startCount, stopCount);
|
||||
|
||||
// Limit to number of cycles if provided
|
||||
if (cycles_set && ((size_t)(numcycles *2) < samples.size()))
|
||||
samples.erase(samples.begin() + (numcycles*2), samples.end());
|
||||
|
||||
// Add setup time (start time)
|
||||
if (samples.empty() || samples.front()!=startCount)
|
||||
samples.insert(samples.begin(), startCount);
|
||||
|
||||
fst->reconstructAllAtTimes(samples);
|
||||
bool initial = true;
|
||||
int cycle = 0;
|
||||
log("Co-simulation from %lu%s to %lu%s\n", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
|
||||
for(auto &time : samples) {
|
||||
log("Co-simulating cycle %d [%lu%s].\n", cycle, (unsigned long)time, fst->getTimescaleString());
|
||||
for(auto &item : inputs) {
|
||||
std::string v = fst->valueAt(item.second, time);
|
||||
top->set_state(item.first, Const::from_string(v));
|
||||
}
|
||||
if (initial) {
|
||||
top->setInitState(time);
|
||||
initial = false;
|
||||
}
|
||||
update();
|
||||
log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
|
||||
if (cycles_set)
|
||||
log(" for %d clock cycle(s)",numcycles);
|
||||
log("\n");
|
||||
bool all_samples = fst_clock.empty();
|
||||
|
||||
bool status = top->checkSignals(time);
|
||||
if (status)
|
||||
log_error("Signal difference\n");
|
||||
cycle++;
|
||||
try {
|
||||
fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
|
||||
log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
|
||||
for(auto &item : inputs) {
|
||||
std::string v = fst->valueOf(item.second);
|
||||
top->set_state(item.first, Const::from_string(v));
|
||||
}
|
||||
|
||||
if (initial) {
|
||||
top->setInitState();
|
||||
write_output_header();
|
||||
initial = false;
|
||||
}
|
||||
update();
|
||||
write_output_step(5*cycle);
|
||||
|
||||
bool status = top->checkSignals();
|
||||
if (status)
|
||||
log_error("Signal difference\n");
|
||||
cycle++;
|
||||
|
||||
// Limit to number of cycles if provided
|
||||
if (cycles_set && cycle > numcycles *2)
|
||||
throw fst_end_of_data_exception();
|
||||
if (time==stopCount)
|
||||
throw fst_end_of_data_exception();
|
||||
});
|
||||
} catch(fst_end_of_data_exception) {
|
||||
// end of data detected
|
||||
}
|
||||
write_output_step(5*(cycle-1)+2);
|
||||
write_output_end();
|
||||
|
||||
if (writeback) {
|
||||
pool<Module*> wbmods;
|
||||
top->writeback(wbmods);
|
||||
|
|
|
|||
Loading…
Reference in New Issue