riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor

This commit is contained in:
Eddie Hung 2019-12-30 20:14:24 -08:00
parent b42b64e8ed 0c4be94a02
commit fad99c2ec7
2 changed files with 4 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
passes/techmap/abc9.cc
View File

@ -124,15 +124,6 @@ struct Abc9Pass : public ScriptPass
log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n"); log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n");
log("if you want to use ABC to convert your design into another format.\n"); log("if you want to use ABC to convert your design into another format.\n");
log("\n"); log("\n");
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("Delay targets can also be specified on a per clock basis by attaching a\n");
log("'(* abc9_period = <int> *)' attribute onto clock wires (specifically, onto wires\n");
log("that appear inside any special '$abc9_clock' wires inserted by abc9_map.v). This\n");
log("can be achieved by modifying the source directly, or through a `setattr`\n");
log("invocation. Since such attributes cannot yet be propagated through a\n");
log("hierarchical design (whether or not it has been uniquified) it is recommended\n");
log("that the design be flattened when using this feature.\n");
log("\n");
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
log("\n"); log("\n");
help_script(); help_script();

8
tests/arch/xilinx/abc9_map.ys
View File

@ -6,7 +6,7 @@ endmodule
EOT EOT
design -save gold design -save gold
techmap -map +/xilinx/abc9_map.v -max_iter 1 techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
techmap -map +/xilinx/abc9_unmap.v techmap -map +/xilinx/abc9_unmap.v
select -assert-count 1 t:FDSE select -assert-count 1 t:FDSE
select -assert-count 1 t:FDSE_1 select -assert-count 1 t:FDSE_1
@ -29,7 +29,7 @@ endmodule
EOT EOT
design -save gold design -save gold
techmap -map +/xilinx/abc9_map.v -max_iter 1 techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
techmap -map +/xilinx/abc9_unmap.v techmap -map +/xilinx/abc9_unmap.v
select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE
select -assert-count 1 t:FDRE_1 select -assert-count 1 t:FDRE_1
@ -52,7 +52,7 @@ endmodule
EOT EOT
design -save gold design -save gold
techmap -map +/xilinx/abc9_map.v -max_iter 1 techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
techmap -map +/xilinx/abc9_unmap.v techmap -map +/xilinx/abc9_unmap.v
select -assert-count 1 t:FDCE select -assert-count 1 t:FDCE
select -assert-count 1 t:FDCE_1 select -assert-count 1 t:FDCE_1
@ -76,7 +76,7 @@ endmodule
EOT EOT
design -save gold design -save gold
techmap -map +/xilinx/abc9_map.v -max_iter 1 techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
techmap -map +/xilinx/abc9_unmap.v techmap -map +/xilinx/abc9_unmap.v
select -assert-count 1 t:FDPE select -assert-count 1 t:FDPE
techmap -autoproc -map +/xilinx/cells_sim.v techmap -autoproc -map +/xilinx/cells_sim.v