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Avoid mixing module port declaration styles in ice40 cells_sim.v 

The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
This commit is contained in:
Olof Kindgren 2018-05-17 13:54:40 +02:00
parent a7281930c5
commit faac2c5595
1 changed files with 23 additions and 43 deletions
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66
techlibs/ice40/cells_sim.v
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@ -1,6 +1,6 @@
`define SB_DFF_REG reg Q = 0; `define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q; // `define SB_DFF_REG reg Q
// SiliconBlue IO Cells // SiliconBlue IO Cells
@ -132,21 +132,18 @@ endmodule
// Positive Edge SiliconBlue FF Cells // Positive Edge SiliconBlue FF Cells
module SB_DFF (output Q, input C, D); module SB_DFF (output `SB_DFF_REG, input C, D);
`SB_DFF_REG
always @(posedge C) always @(posedge C)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFE (output Q, input C, E, D); module SB_DFFE (output `SB_DFF_REG, input C, E, D);
`SB_DFF_REG
always @(posedge C) always @(posedge C)
if (E) if (E)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFSR (output Q, input C, R, D); module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
`SB_DFF_REG
always @(posedge C) always @(posedge C)
if (R) if (R)
Q <= 0; Q <= 0;
@ -154,8 +151,7 @@ module SB_DFFSR (output Q, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFR (output Q, input C, R, D); module SB_DFFR (output `SB_DFF_REG, input C, R, D);
`SB_DFF_REG
always @(posedge C, posedge R) always @(posedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -163,8 +159,7 @@ module SB_DFFR (output Q, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFSS (output Q, input C, S, D); module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
`SB_DFF_REG
always @(posedge C) always @(posedge C)
if (S) if (S)
Q <= 1; Q <= 1;
@ -172,8 +167,7 @@ module SB_DFFSS (output Q, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFS (output Q, input C, S, D); module SB_DFFS (output `SB_DFF_REG, input C, S, D);
`SB_DFF_REG
always @(posedge C, posedge S) always @(posedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -181,8 +175,7 @@ module SB_DFFS (output Q, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFESR (output Q, input C, E, R, D); module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
`SB_DFF_REG
always @(posedge C) always @(posedge C)
if (E) begin if (E) begin
if (R) if (R)
@ -192,8 +185,7 @@ module SB_DFFESR (output Q, input C, E, R, D);
end end
endmodule endmodule
module SB_DFFER (output Q, input C, E, R, D); module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
`SB_DFF_REG
always @(posedge C, posedge R) always @(posedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -201,8 +193,7 @@ module SB_DFFER (output Q, input C, E, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFESS (output Q, input C, E, S, D); module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
`SB_DFF_REG
always @(posedge C) always @(posedge C)
if (E) begin if (E) begin
if (S) if (S)
@ -212,8 +203,7 @@ module SB_DFFESS (output Q, input C, E, S, D);
end end
endmodule endmodule
module SB_DFFES (output Q, input C, E, S, D); module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
`SB_DFF_REG
always @(posedge C, posedge S) always @(posedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -223,21 +213,18 @@ endmodule
// Negative Edge SiliconBlue FF Cells // Negative Edge SiliconBlue FF Cells
module SB_DFFN (output Q, input C, D); module SB_DFFN (output `SB_DFF_REG, input C, D);
`SB_DFF_REG
always @(negedge C) always @(negedge C)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNE (output Q, input C, E, D); module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
`SB_DFF_REG
always @(negedge C) always @(negedge C)
if (E) if (E)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNSR (output Q, input C, R, D); module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
`SB_DFF_REG
always @(negedge C) always @(negedge C)
if (R) if (R)
Q <= 0; Q <= 0;
@ -245,8 +232,7 @@ module SB_DFFNSR (output Q, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNR (output Q, input C, R, D); module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
`SB_DFF_REG
always @(negedge C, posedge R) always @(negedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -254,8 +240,7 @@ module SB_DFFNR (output Q, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNSS (output Q, input C, S, D); module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
`SB_DFF_REG
always @(negedge C) always @(negedge C)
if (S) if (S)
Q <= 1; Q <= 1;
@ -263,8 +248,7 @@ module SB_DFFNSS (output Q, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNS (output Q, input C, S, D); module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
`SB_DFF_REG
always @(negedge C, posedge S) always @(negedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -272,8 +256,7 @@ module SB_DFFNS (output Q, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNESR (output Q, input C, E, R, D); module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
`SB_DFF_REG
always @(negedge C) always @(negedge C)
if (E) begin if (E) begin
if (R) if (R)
@ -283,8 +266,7 @@ module SB_DFFNESR (output Q, input C, E, R, D);
end end
endmodule endmodule
module SB_DFFNER (output Q, input C, E, R, D); module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
`SB_DFF_REG
always @(negedge C, posedge R) always @(negedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -292,8 +274,7 @@ module SB_DFFNER (output Q, input C, E, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNESS (output Q, input C, E, S, D); module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
`SB_DFF_REG
always @(negedge C) always @(negedge C)
if (E) begin if (E) begin
if (S) if (S)
@ -303,8 +284,7 @@ module SB_DFFNESS (output Q, input C, E, S, D);
end end
endmodule endmodule
module SB_DFFNES (output Q, input C, E, S, D); module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
`SB_DFF_REG
always @(negedge C, posedge S) always @(negedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -677,7 +657,7 @@ module ICESTORM_LC (
parameter [0:0] SET_NORESET = 0; parameter [0:0] SET_NORESET = 0;
parameter [0:0] ASYNC_SR = 0; parameter [0:0] ASYNC_SR = 0;
wire COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx; assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx;
wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];