riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Some minor build fixes for Visual C

This commit is contained in:
Clifford Wolf 2016-10-14 18:34:44 +02:00
parent e4c5ee9b89
commit fa535c0b00
3 changed files with 16 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
kernel/driver.cc
View File

@ -510,7 +510,9 @@ int main(int argc, char **argv)
#endif
log_flush();
#ifdef _WIN32
#if defined(_MSC_VER)
_exit(0);
#elif defined(_WIN32)
_Exit(0);
#endif

2
kernel/log.cc
View File

@ -207,6 +207,8 @@ void logv_error(const char *format, va_list ap)
#ifdef EMSCRIPTEN
log_files = backup_log_files;
throw 0;
#elif defined(_MSC_VER)
_exit(1);
#else
_Exit(1);
#endif

13
passes/sat/clk2fflogic.cc
View File

@ -93,8 +93,17 @@ struct Clk2fflogicPass : public Pass {
log_signal(clk), log_signal(sig_d), log_signal(sig_q));
module->remove(cell);
SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk},
clkpol ? SigSpec({State::S0, State::S1}) : SigSpec({State::S1, State::S0}));
SigSpec clock_edge_pattern;
if (clkpol) {
clock_edge_pattern.append_bit(State::S0);
clock_edge_pattern.append_bit(State::S1);
} else {
clock_edge_pattern.append_bit(State::S1);
clock_edge_pattern.append_bit(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk}, clock_edge_pattern);
Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));