mirror of https://github.com/YosysHQ/yosys.git
Fix broken test when ignoring abc9_flop with init == 1'b1
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97a0a04314
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@ -213,7 +213,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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if (init != State::S0) {
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if (init != State::S0) {
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log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
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log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
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derived_module->set_bool_attribute(ID::abc9_flop, false);
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derived_module->set_bool_attribute(ID::abc9_flop, false);
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goto skip_cell;
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}
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}
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break;
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break;
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}
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}
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@ -250,8 +249,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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cell->type = derived_type;
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cell->type = derived_type;
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cell->parameters.clear();
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cell->parameters.clear();
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skip_cell: ;
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}
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}
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}
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}
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