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Added generic RTLIL::SigSpec::parse_sel() with support for selection variables

This commit is contained in:
Clifford Wolf 2014-02-06 19:22:46 +01:00
parent d4b0f28881
commit fa295a4528
5 changed files with 39 additions and 37 deletions
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18
kernel/rtlil.cc
View File

@ -1649,6 +1649,24 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
return true; return true;
} }
bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
{
if (str.empty() || str[0] != '@')
return parse(sig, module, str);
str = RTLIL::escape_id(str.substr(1));
if (design->selection_vars.count(str) == 0)
return false;
sig = RTLIL::SigSpec();
RTLIL::Selection &sel = design->selection_vars.at(str);
for (auto &it : module->wires)
if (sel.selected_member(module->name, it.first))
sig.append(it.second);
return true;
}
bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str) bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
{ {
if (str == "0") { if (str == "0") {

1
kernel/rtlil.h
View File

@ -411,6 +411,7 @@ struct RTLIL::SigSpec {
std::vector<RTLIL::SigBit> to_sigbit_vector() const; std::vector<RTLIL::SigBit> to_sigbit_vector() const;
RTLIL::SigBit to_single_sigbit() const; RTLIL::SigBit to_single_sigbit() const;
static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
}; };

6
passes/cmds/connect.cc
View File

@ -137,7 +137,7 @@ struct ConnectPass : public Pass {
log_cmd_error("Cant use -set together with -unset and/or -port.\n"); log_cmd_error("Cant use -set together with -unset and/or -port.\n");
RTLIL::SigSpec sig_lhs, sig_rhs; RTLIL::SigSpec sig_lhs, sig_rhs;
if (!RTLIL::SigSpec::parse(sig_lhs, module, set_lhs)) if (!RTLIL::SigSpec::parse_sel(sig_lhs, design, module, set_lhs))
log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs.c_str()); log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs.c_str());
if (!RTLIL::SigSpec::parse_rhs(sig_lhs, sig_rhs, module, set_rhs)) if (!RTLIL::SigSpec::parse_rhs(sig_lhs, sig_rhs, module, set_rhs))
log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs.c_str()); log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs.c_str());
@ -157,7 +157,7 @@ struct ConnectPass : public Pass {
log_cmd_error("Cant use -unset together with -port and/or -nounset.\n"); log_cmd_error("Cant use -unset together with -port and/or -nounset.\n");
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, unset_expr)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, unset_expr))
log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr.c_str()); log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr.c_str());
sigmap.apply(sig); sigmap.apply(sig);
@ -173,7 +173,7 @@ struct ConnectPass : public Pass {
log_cmd_error("Can't find cell %s.\n", port_cell.c_str()); log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, port_expr)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
module->cells.at(RTLIL::escape_id(port_cell))->connections[RTLIL::escape_id(port_port)] = sigmap(sig); module->cells.at(RTLIL::escape_id(port_cell))->connections[RTLIL::escape_id(port_port)] = sigmap(sig);

8
passes/sat/eval.cc
View File

@ -464,7 +464,7 @@ struct EvalPass : public Pass {
for (auto &it : sets) { for (auto &it : sets) {
RTLIL::SigSpec lhs, rhs; RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse(lhs, module, it.first)) if (!RTLIL::SigSpec::parse_sel(lhs, design, module, it.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str()); log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str());
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second)) if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str()); log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
@ -486,7 +486,7 @@ struct EvalPass : public Pass {
{ {
for (auto &it : shows) { for (auto &it : shows) {
RTLIL::SigSpec signal, value, undef; RTLIL::SigSpec signal, value, undef;
if (!RTLIL::SigSpec::parse(signal, module, it)) if (!RTLIL::SigSpec::parse_sel(signal, design, module, it))
log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
signal.optimize(); signal.optimize();
value = signal; value = signal;
@ -513,14 +513,14 @@ struct EvalPass : public Pass {
for (auto &it : shows) { for (auto &it : shows) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, it)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
signal.append(sig); signal.append(sig);
} }
for (auto &it : tables) { for (auto &it : tables) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, it)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str()); log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str());
tabsigs.append(sig); tabsigs.append(sig);
} }

43
passes/sat/sat.cc
View File

@ -111,7 +111,7 @@ struct SatHelper
{ {
RTLIL::SigSpec lhs, rhs; RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse(lhs, module, s.first)) if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
@ -180,7 +180,7 @@ struct SatHelper
{ {
RTLIL::SigSpec lhs, rhs; RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse(lhs, module, s.first)) if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
@ -201,7 +201,7 @@ struct SatHelper
{ {
RTLIL::SigSpec lhs, rhs; RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse(lhs, module, s.first)) if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
@ -222,7 +222,7 @@ struct SatHelper
{ {
RTLIL::SigSpec lhs; RTLIL::SigSpec lhs;
if (!RTLIL::SigSpec::parse(lhs, module, s)) if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str());
show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(lhs));
@ -241,28 +241,28 @@ struct SatHelper
for (auto &s : sets_def) { for (auto &s : sets_def) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, s)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
sets_def_undef[0].insert(sig); sets_def_undef[0].insert(sig);
} }
for (auto &s : sets_any_undef) { for (auto &s : sets_any_undef) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, s)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
sets_def_undef[1].insert(sig); sets_def_undef[1].insert(sig);
} }
for (auto &s : sets_all_undef) { for (auto &s : sets_all_undef) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, s)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
sets_def_undef[2].insert(sig); sets_def_undef[2].insert(sig);
} }
for (auto &s : sets_def_at[timestep]) { for (auto &s : sets_def_at[timestep]) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, s)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
sets_def_undef[0].insert(sig); sets_def_undef[0].insert(sig);
sets_def_undef[1].erase(sig); sets_def_undef[1].erase(sig);
@ -271,7 +271,7 @@ struct SatHelper
for (auto &s : sets_any_undef_at[timestep]) { for (auto &s : sets_any_undef_at[timestep]) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, s)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
sets_def_undef[0].erase(sig); sets_def_undef[0].erase(sig);
sets_def_undef[1].insert(sig); sets_def_undef[1].insert(sig);
@ -280,7 +280,7 @@ struct SatHelper
for (auto &s : sets_all_undef_at[timestep]) { for (auto &s : sets_all_undef_at[timestep]) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, s)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
sets_def_undef[0].erase(sig); sets_def_undef[0].erase(sig);
sets_def_undef[1].erase(sig); sets_def_undef[1].erase(sig);
@ -329,7 +329,7 @@ struct SatHelper
{ {
RTLIL::SigSpec lhs, rhs; RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse(lhs, module, s.first)) if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first.c_str()); log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first.c_str());
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second.c_str()); log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second.c_str());
@ -357,7 +357,7 @@ struct SatHelper
{ {
RTLIL::SigSpec lhs, rhs; RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse(lhs, module, s.first)) if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first.c_str()); log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first.c_str());
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second.c_str()); log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second.c_str());
@ -509,7 +509,7 @@ struct SatHelper
{ {
for (auto &s : shows) { for (auto &s : shows) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse(sig, module, s)) if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str()); log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str());
log("Import show expression: %s\n", log_signal(sig)); log("Import show expression: %s\n", log_signal(sig));
modelSig.append(sig); modelSig.append(sig);
@ -733,10 +733,6 @@ struct SatPass : public Pass {
log(" show the model for the specified signal. if no -show option is\n"); log(" show the model for the specified signal. if no -show option is\n");
log(" passed then a set of signals to be shown is automatically selected.\n"); log(" passed then a set of signals to be shown is automatically selected.\n");
log("\n"); log("\n");
log(" -show @<sel_name>\n");
log(" add all wires from the specified selection (see help select) to\n");
log(" the list of signals to be shown.\n");
log("\n");
log(" -show-inputs, -show-outputs\n"); log(" -show-inputs, -show-outputs\n");
log(" add all module input (output) ports to the list of shown signals\n"); log(" add all module input (output) ports to the list of shown signals\n");
log("\n"); log("\n");
@ -1026,19 +1022,6 @@ struct SatPass : public Pass {
sets_def.push_back(it.second->name); sets_def.push_back(it.second->name);
} }
for (auto &str : shows) {
if (str.empty() || str[0] != '@')
continue;
str = RTLIL::escape_id(str.substr(1));
if (design->selection_vars.count(str) == 0)
log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str));
RTLIL::Selection &sel = design->selection_vars.at(str);
str.clear();
for (auto &it : module->wires)
if (sel.selected_member(module->name, it.first))
str += (str.empty() ? "" : ",") + it.first;
}
if (show_inputs) { if (show_inputs) {
for (auto &it : module->wires) for (auto &it : module->wires)
if (it.second->port_input) if (it.second->port_input)