mirror of https://github.com/YosysHQ/yosys.git
synth_xilinx to use shregmap with -minlen 3
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@ -114,7 +114,7 @@ struct SynthXilinxPass : public Pass
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log(" dff2dffe\n");
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log(" dff2dffe\n");
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log(" opt -full\n");
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log(" opt -full\n");
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log(" simplemap t:$dff* (only without -nosrl)\n");
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log(" simplemap t:$dff* (only without -nosrl)\n");
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log(" shregmap -tech xilinx (only without -nosrl)\n");
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log(" shregmap -tech xilinx -minlen 3 (only without -nosrl)\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
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log(" opt -fast\n");
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log(" opt -fast\n");
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log("\n");
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log("\n");
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@ -267,7 +267,7 @@ struct SynthXilinxPass : public Pass
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if (!nosrl) {
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if (!nosrl) {
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Pass::call(design, "simplemap t:$dff*");
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Pass::call(design, "simplemap t:$dff*");
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Pass::call(design, "shregmap -tech xilinx");
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Pass::call(design, "shregmap -tech xilinx -minlen 3");
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}
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}
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if (vpr) {
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if (vpr) {
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