mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: add "-print-output" option, test in fmt
This commit is contained in:
parent
bfa8b631bf
commit
f9b149fa7b
|
@ -682,6 +682,7 @@ struct CxxrtlWorker {
|
|||
bool split_intf = false;
|
||||
std::string intf_filename;
|
||||
std::string design_ns = "cxxrtl_design";
|
||||
std::string print_output = "std::cout";
|
||||
std::ostream *impl_f = nullptr;
|
||||
std::ostream *intf_f = nullptr;
|
||||
|
||||
|
@ -1042,8 +1043,7 @@ struct CxxrtlWorker {
|
|||
Fmt fmt = {};
|
||||
fmt.parse_rtlil(cell);
|
||||
|
||||
// TODO: we may want to configure the output stream
|
||||
f << indent << "std::cout";
|
||||
f << indent << print_output;
|
||||
fmt.emit_cxxrtl(f, [this](const RTLIL::SigSpec &sig) { dump_sigspec_rhs(sig); });
|
||||
f << ";\n";
|
||||
}
|
||||
|
@ -3263,6 +3263,10 @@ struct CxxrtlBackend : public Backend {
|
|||
log(" place the generated code into namespace <ns-name>. if not specified,\n");
|
||||
log(" \"cxxrtl_design\" is used.\n");
|
||||
log("\n");
|
||||
log(" -print-output <stream>\n");
|
||||
log(" $print cells in the generated code direct their output to <stream>.\n");
|
||||
log(" if not specified, \"std::cout\" is used.\n");
|
||||
log("\n");
|
||||
log(" -nohierarchy\n");
|
||||
log(" use design hierarchy as-is. in most designs, a top module should be\n");
|
||||
log(" present as it is exposed through the C API and has unbuffered outputs\n");
|
||||
|
@ -3401,6 +3405,10 @@ struct CxxrtlBackend : public Backend {
|
|||
worker.design_ns = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-print-output" && argidx+1 < args.size()) {
|
||||
worker.print_output = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
|
|
@ -47,9 +47,9 @@ test_roundtrip oct_signed -DBASE_HEX -DSIGN="signed"
|
|||
test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=""
|
||||
test_roundtrip bin_signed -DBASE_HEX -DSIGN="signed"
|
||||
|
||||
../../yosys -p "read_verilog always_full.v; write_cxxrtl yosys-always_full.cc"
|
||||
../../yosys -p "read_verilog always_full.v; write_cxxrtl -print-output std::cerr yosys-always_full.cc"
|
||||
${CXX:-g++} -o yosys-always_full -I../.. always_full_tb.cc
|
||||
./yosys-always_full >yosys-always_full.log
|
||||
./yosys-always_full 2>yosys-always_full.log
|
||||
iverilog -o iverilog-always_full always_full.v always_full_tb.v
|
||||
./iverilog-always_full | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >iverilog-always_full.log
|
||||
diff iverilog-always_full.log yosys-always_full.log
|
||||
|
|
Loading…
Reference in New Issue