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Another typo
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@ -112,7 +112,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
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endgenerate
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, CLR);
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDPE_1 #(
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