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read_aiger: new naming fixes

This commit is contained in:
Eddie Hung 2019-02-20 12:39:51 -08:00
parent 83b66861e9
commit f9702a8abe
1 changed files with 5 additions and 5 deletions
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10
frontends/aiger/aigerparse.cc
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@ -347,8 +347,8 @@ void AigerReader::parse_xaiger()
module->rename(wire, stringf("\\%s", s.c_str())); module->rename(wire, stringf("\\%s", s.c_str()));
RTLIL::Cell* driver = module->cell(stringf("%s_lut", wire->name.c_str())); RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
module->rename(driver, stringf("%s_lut", wire->name.c_str())); module->rename(driver, stringf("%slut", wire->name.c_str()));
std::getline(f, line); // Ignore up to start of next line std::getline(f, line); // Ignore up to start of next line
++line_count; ++line_count;
@ -385,7 +385,7 @@ void AigerReader::parse_xaiger()
log_assert(wire); log_assert(wire);
log_assert(wire->port_output); log_assert(wire->port_output);
RTLIL::Cell* driver = module->cell(stringf("%s_lut", wire->name.c_str())); RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
if (index == 0) if (index == 0)
module->rename(wire, RTLIL::escape_id(symbol)); module->rename(wire, RTLIL::escape_id(symbol));
@ -396,7 +396,7 @@ void AigerReader::parse_xaiger()
} }
if (driver) if (driver)
module->rename(driver, stringf("%s_lut", wire->name.c_str())); module->rename(driver, stringf("%slut", wire->name.c_str()));
} }
else else
log_error("Symbol type '%s' not recognised.\n", type.c_str()); log_error("Symbol type '%s' not recognised.\n", type.c_str());
@ -656,7 +656,7 @@ void AigerReader::parse_aiger_binary()
log_debug("%d is an output\n", l1); log_debug("%d is an output\n", l1);
const unsigned variable = l1 >> 1; const unsigned variable = l1 >> 1;
const bool invert = l1 & 1; const bool invert = l1 & 1;
RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "_b" : "")); // FIXME: is "_inv" the right suffix? RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_inv" the right suffix?
wire = module->wire(wire_name); wire = module->wire(wire_name);
if (!wire) if (!wire)
wire = createWireIfNotExists(module, l1); wire = createWireIfNotExists(module, l1);