riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add -nocarry option to synth_xilinx

This commit is contained in:
Eddie Hung 2019-04-24 16:46:41 -07:00
parent bfd71e0990
commit f96d82a5f1
1 changed files with 14 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
techlibs/xilinx/synth_xilinx.cc
View File

@ -63,6 +63,9 @@ struct SynthXilinxPass : public Pass
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
log(" -nocarry\n");
log(" disable inference of carry chains\n");
log("\n");
log(" -nobram\n");
log(" disable inference of block rams\n");
log("\n");
@ -118,7 +121,7 @@ struct SynthXilinxPass : public Pass
log(" memory_map\n");
log(" dffsr2dff\n");
log(" dff2dffe\n");
log(" techmap -map +/xilinx/arith_map.v\n");
log(" techmap -map +/xilinx/arith_map.v (without '-nocarry' only)\n");
log(" opt -fast\n");
log("\n");
log(" map_cells:\n");
@ -161,6 +164,7 @@ struct SynthXilinxPass : public Pass
bool flatten = false;
bool retime = false;
bool vpr = false;
bool nocarry = false;
bool nobram = false;
bool nodram = false;
bool nosrl = false;
@ -201,6 +205,10 @@ struct SynthXilinxPass : public Pass
vpr = true;
continue;
}
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
@ -284,9 +292,10 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "dffsr2dff");
Pass::call(design, "dff2dffe");
if (vpr) {
if (!nocarry) {
if (vpr)
Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
} else {
else
Pass::call(design, "techmap -map +/xilinx/arith_map.v");
}