mirror of https://github.com/YosysHQ/yosys.git
passes/hierarchy: Reduce code duplication in expand_module
This also makes it easier to add new file extensions support. Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
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77bd645c35
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@ -173,22 +173,20 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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for (auto &dir : libdirs)
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for (auto &dir : libdirs)
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{
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{
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
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static const std::map<std::string, std::string> extensions_map =
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{
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{".v", "verilog"},
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{".sv", "verilog -sv"},
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{".il", "ilang"}
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};
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for (auto &ext : extensions_map)
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{
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ext.first;
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if (check_file_exists(filename)) {
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if (check_file_exists(filename)) {
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Frontend::frontend_call(design, NULL, filename, "verilog");
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Frontend::frontend_call(design, NULL, filename, ext.second);
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goto loaded_module;
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goto loaded_module;
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}
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}
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".sv";
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if (check_file_exists(filename)) {
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Frontend::frontend_call(design, NULL, filename, "verilog -sv");
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goto loaded_module;
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}
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
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if (check_file_exists(filename)) {
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Frontend::frontend_call(design, NULL, filename, "ilang");
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goto loaded_module;
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}
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}
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}
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}
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