From aff0065646f1f526c199bdbb8de74f22391a345d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 21 Jun 2023 13:21:34 +0200 Subject: [PATCH] Use defaultvalue for init values of input ports --- frontends/verific/verific.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 52008ddc6..989e2173b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2005,7 +2005,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma initval[i] = State::Sx; } - if (initval.is_fully_undef()) + if (wire->port_input) { + wire->attributes[ID::defaultvalue] = Const(initval); + wire->attributes.erase(ID::init); + } else if (initval.is_fully_undef()) wire->attributes.erase(ID::init); } }