riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Missed this

This commit is contained in:
Eddie Hung 2019-10-05 08:57:37 -07:00
parent 991c2ca95b
commit f90a4b1e24
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
passes/pmgen/xilinx_dsp_CREG.pmg
View File

@ -105,9 +105,10 @@ endcode
// ####################### // #######################
// Subpattern for matching against input registers, based on knowledge of the // Subpattern for matching against input registers, based on knowledge of the
// 'Q' input. Typically, this task would be handled by other Yosys passes // 'Q' input. Typically, identifying registers with clock-enable and reset
// such as dff2dffe, but since DSP inference happens much before this, these // capability would be a task would be handled by other Yosys passes such as
// patterns have to be manually identified. // dff2dffe, but since DSP inference happens much before this, these patterns
// have to be manually identified.
// At a high level: // At a high level:
// (1) Starting from a $dff cell that (partially or fully) drives the given // (1) Starting from a $dff cell that (partially or fully) drives the given
// 'Q' argument // 'Q' argument