Manual fixes for new cell connections API

backends/btor/btor.cc

@@ -193,7 +193,7 @@ struct BtorDumper
 						break;
 					log(" -- found cell %s\n", cstr(cell_id));
 					RTLIL::Cell* cell = module->cells.at(cell_id);
-					RTLIL::SigSpec* cell_output = get_cell_output(cell);
+					const RTLIL::SigSpec* cell_output = get_cell_output(cell);
 					int cell_line = dump_cell(cell);				
 
 					if(dep_set.size()==1 && wire->width == cell_output->size())
@@ -796,9 +796,9 @@ struct BtorDumper
 		}
 	}
 
-	RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
+	const RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
 	{
-		RTLIL::SigSpec *output_sig = nullptr;
+		const RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
 			output_sig = &cell->connections().at(RTLIL::IdString("\\DATA"));
@@ -835,7 +835,7 @@ struct BtorDumper
 		for (auto it = module->cells.begin(); it != module->cells.end(); ++it)
 		{
 			RTLIL::Cell *cell = it->second;
-			RTLIL::SigSpec* output_sig = get_cell_output(cell);
+			const RTLIL::SigSpec* output_sig = get_cell_output(cell);
 			if(output_sig==nullptr)
 				continue;
 			RTLIL::SigSpec s = sigmap(*output_sig);

backends/verilog/verilog_backend.cc

@@ -223,7 +223,7 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals
 	}
 }
 
-void dump_sigspec(FILE *f, RTLIL::SigSpec &sig)
+void dump_sigspec(FILE *f, const RTLIL::SigSpec &sig)
 {
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk());
@@ -293,10 +293,10 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
 {
 	if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) {
 		fprintf(f, "$signed(");
-		dump_sigspec(f, cell->connections()["\\" + port]);
+		dump_sigspec(f, cell->get("\\" + port));
 		fprintf(f, ")");
 	} else
-		dump_sigspec(f, cell->connections()["\\" + port]);
+		dump_sigspec(f, cell->get("\\" + port));
 }
 
 std::string cellname(RTLIL::Cell *cell)
@@ -735,7 +735,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
 	fprintf(f, "\n%s" ");\n", indent.c_str());
 }
 
-void dump_conn(FILE *f, std::string indent, RTLIL::SigSpec &left, RTLIL::SigSpec &right)
+void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
 	fprintf(f, "%s" "assign ", indent.c_str());
 	dump_sigspec(f, left);

frontends/ast/genrtlil.cc

@@ -1297,9 +1297,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					if (child->str.size() == 0) {
 						char buf[100];
 						snprintf(buf, 100, "$%d", ++port_counter);
-						cell->connections()[buf] = sig;
+						cell->set(buf, sig);
 					} else {
-						cell->connections()[child->str] = sig;
+						cell->set(child->str, sig);
 					}
 					continue;
 				}

frontends/ilang/parser.y

@@ -204,7 +204,7 @@ cell_body:
 	cell_body TOK_CONNECT TOK_ID sigspec EOL {
 		if (current_cell->connections().count($3) != 0)
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
-		current_cell->connections()[$3] = *$4;
+		current_cell->set($3, *$4);
 		delete $4;
 		free($3);
 	} |

kernel/rtlil.cc

@@ -773,7 +773,7 @@ void RTLIL::Module::optimize()
 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 {
 	new_mod->name = name;
-	new_mod->connections() = connections_;
+	new_mod->connections_ = connections_;
 	new_mod->attributes = attributes;
 
 	for (auto &it : wires)
@@ -924,7 +924,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
 {
 	RTLIL::Cell *cell = addCell(name, other->type);
-	cell->connections() = other->connections();
+	cell->connections_ = other->connections_;
 	cell->parameters = other->parameters;
 	cell->attributes = other->attributes;
 	return cell;
@@ -1036,8 +1036,8 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections()["\\" #_P1] = sig1;        \
+		cell->set("\\" #_P1, sig1);                 \
-		cell->connections()["\\" #_P2] = sig2;        \
+		cell->set("\\" #_P2, sig2);                 \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1051,9 +1051,9 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections()["\\" #_P1] = sig1;        \
+		cell->set("\\" #_P1, sig1);                 \
-		cell->connections()["\\" #_P2] = sig2;        \
+		cell->set("\\" #_P2, sig2);                 \
-		cell->connections()["\\" #_P3] = sig3;        \
+		cell->set("\\" #_P3, sig3);                 \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1067,10 +1067,10 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections()["\\" #_P1] = sig1;        \
+		cell->set("\\" #_P1, sig1);                 \
-		cell->connections()["\\" #_P2] = sig2;        \
+		cell->set("\\" #_P2, sig2);                 \
-		cell->connections()["\\" #_P3] = sig3;        \
+		cell->set("\\" #_P3, sig3);                 \
-		cell->connections()["\\" #_P4] = sig4;        \
+		cell->set("\\" #_P4, sig4);                 \
 		add(cell);                                  \
 		return cell;                                \
 	} \

passes/abc/abc.cc

@@ -785,7 +785,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 						assert(c.width == 1);
 						newsig.append(module->wires[remap_name(c.wire->name)]);
 					}
-					cell->connections()[conn.first] = newsig;
+					cell->set(conn.first, newsig);
 				}
 				design->select(module, cell);
 			}

passes/abc/blifparse.cc

@@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 					*(q++) = 0;
 					if (module->wires.count(RTLIL::escape_id(q)) == 0)
 						module->addWire(RTLIL::escape_id(q));
-					cell->connections()[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
+					cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q)));
 				}
 				continue;
 			}

passes/cmds/add.cc

@@ -78,7 +78,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 		if (it.second->connections().count(name) > 0)
 			continue;
 
-		it.second->connections()[name] = wire;
+		it.second->set(name, wire);
 		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
 	}
 }

passes/cmds/connect.cc

@@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
 
 	for (auto &it : module->cells)
-	for (auto &port : it.second->connections())
+	for (auto &port : it.second->connections_)
 		if (ct.cell_output(it.second->type, port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 
-	for (auto &conn : module->connections())
+	for (auto &conn : module->connections_)
 		sigmap(conn.first).replace(sig, dummy_wire, &conn.first);
 }
 
@@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
 				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
 
-			module->cells.at(RTLIL::escape_id(port_cell))->connections()[RTLIL::escape_id(port_port)] = sigmap(sig);
+			module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
 		}
 		else
 			log_cmd_error("Expected -set, -unset, or -port.\n");

passes/cmds/connwrappers.cc

@@ -109,7 +109,7 @@ struct ConnwrappersWorker
 			if (!design->selected(module, cell))
 				continue;
 
-			for (auto &conn : cell->connections())
+			for (auto &conn : cell->connections_)
 			{
 				std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
 				RTLIL::SigSpec old_sig;

passes/cmds/scatter.cc

@@ -49,7 +49,7 @@ struct ScatterPass : public Pass {
 				continue;
 
 			for (auto &c : mod_it.second->cells)
-			for (auto &p : c.second->connections())
+			for (auto &p : c.second->connections_)
 			{
 				RTLIL::Wire *wire = new RTLIL::Wire;
 				wire->name = NEW_ID;

passes/cmds/show.cc

@@ -87,17 +87,17 @@ struct ShowWorker
 		return defaultColor;
 	}
 
-	std::string nextColor(RTLIL::SigSig &conn, std::string defaultColor)
+	std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor)
 	{
 		return nextColor(conn.first, nextColor(conn.second, defaultColor));
 	}
 
-	std::string nextColor(RTLIL::SigSpec &sig)
+	std::string nextColor(const RTLIL::SigSpec &sig)
 	{
 		return nextColor(sig, nextColor());
 	}
 
-	std::string nextColor(RTLIL::SigSig &conn)
+	std::string nextColor(const RTLIL::SigSig &conn)
 	{
 		return nextColor(conn, nextColor());
 	}

passes/cmds/splice.cc

@@ -182,7 +182,7 @@ struct SpliceWorker
 		for (auto &it : module->cells) {
 			if (!sel_by_wire && !design->selected(module, it.second))
 				continue;
-			for (auto &conn : it.second->connections())
+			for (auto &conn : it.second->connections_)
 				if (ct.cell_input(it.second->type, conn.first)) {
 					if (ports.size() > 0 && !ports.count(conn.first))
 						continue;

passes/fsm/fsm_expand.cc

@@ -167,10 +167,14 @@ struct FsmExpand
 		fsm_data.copy_from_cell(fsm_cell);
 
 		fsm_data.num_inputs += input_sig.size();
-		fsm_cell->get("\\CTRL_IN").append(input_sig);
+		RTLIL::SigSpec new_ctrl_in = fsm_cell->get("\\CTRL_IN");
+		new_ctrl_in.append(input_sig);
+		fsm_cell->set("\\CTRL_IN", new_ctrl_in);
 
 		fsm_data.num_outputs += output_sig.size();
-		fsm_cell->get("\\CTRL_OUT").append(output_sig);
+		RTLIL::SigSpec new_ctrl_out = fsm_cell->get("\\CTRL_OUT");
+		new_ctrl_out.append(output_sig);
+		fsm_cell->set("\\CTRL_OUT", new_ctrl_out);
 
 		std::vector<FsmData::transition_t> new_transition_table;
 		for (auto &tr : fsm_data.transition_table) {

passes/fsm/fsm_extract.cc

@@ -294,13 +294,13 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2driver.find(ctrl_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells.at(cellport.first);
-		RTLIL::SigSpec port_sig = assign_map(cell->connections()[cellport.second]);
+		RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
 		RTLIL::Wire *unconn_wire = new RTLIL::Wire;
 		unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
 		unconn_wire->width = unconn_sig.size();
 		module->wires[unconn_wire->name] = unconn_wire;
-		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections()[cellport.second]);
+		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
 	}
 }
 

passes/fsm/fsm_opt.cc

@@ -79,7 +79,9 @@ struct FsmOpt
 					tmp.remove(i, 1);
 					tr.ctrl_in = tmp.as_const();
 				}
-				cell->get("\\CTRL_IN").remove(i, 1);
+				RTLIL::SigSpec new_ctrl_in = cell->get("\\CTRL_IN");
+				new_ctrl_in.remove(i, 1);
+				cell->set("\\CTRL_IN", new_ctrl_in);
 				fsm_data.num_inputs--;
 			}
 		}
@@ -94,7 +96,9 @@ struct FsmOpt
 			RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1);
 			if (signal_is_unused(sig)) {
 				log("  Removing unused output signal %s.\n", log_signal(sig));
-				cell->get("\\CTRL_OUT").remove(i, 1);
+				RTLIL::SigSpec new_ctrl_out = cell->get("\\CTRL_OUT");
+				new_ctrl_out.remove(i, 1);
+				cell->set("\\CTRL_OUT", new_ctrl_out);
 				for (auto &tr : fsm_data.transition_table) {
 					RTLIL::SigSpec tmp(tr.ctrl_out);
 					tmp.remove(i, 1);
@@ -108,7 +112,7 @@ struct FsmOpt
 
 	void opt_alias_inputs()
 	{
-		RTLIL::SigSpec &ctrl_in = cell->get("\\CTRL_IN");
+		RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
 
 		for (int i = 0; i < ctrl_in.size(); i++)
 		for (int j = i+1; j < ctrl_in.size(); j++)
@@ -145,8 +149,8 @@ struct FsmOpt
 
 	void opt_feedback_inputs()
 	{
-		RTLIL::SigSpec &ctrl_in = cell->get("\\CTRL_IN");
+		RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
-		RTLIL::SigSpec &ctrl_out = cell->get("\\CTRL_OUT");
+		RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"];
 
 		for (int j = 0; j < ctrl_out.size(); j++)
 		for (int i = 0; i < ctrl_in.size(); i++)

passes/hierarchy/hierarchy.cc

@@ -219,7 +219,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 
 		RTLIL::Module *mod = design->modules[cell->type];
 
-		for (auto &conn : cell->connections()) {
+		for (auto &conn : cell->connections_) {
 			int conn_size = conn.second.size();
 			std::string portname = conn.first;
 			if (portname.substr(0, 1) == "$") {
@@ -519,7 +519,7 @@ struct HierarchyPass : public Pass {
 							new_connections[pos_map.at(key)] = conn.second;
 					} else
 						new_connections[conn.first] = conn.second;
-				cell->connections() = new_connections;
+				cell->connections_ = new_connections;
 			}
 		}
 

passes/hierarchy/submod.cc

@@ -65,7 +65,7 @@ struct SubmodWorker
 		flag_found_something = true;
 	}
 
-	void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
+	void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
 	{
 		for (auto &c : sig.chunks())
 			if (c.wire != NULL)
@@ -163,7 +163,7 @@ struct SubmodWorker
 
 		for (RTLIL::Cell *cell : submod.cells) {
 			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
-			for (auto &conn : new_cell->connections())
+			for (auto &conn : new_cell->connections_)
 				for (auto &bit : conn.second)
 					if (bit.wire != NULL) {
 						assert(wire_flags.count(bit.wire) > 0);
@@ -180,7 +180,7 @@ struct SubmodWorker
 			RTLIL::Wire *old_wire = it.first;
 			RTLIL::Wire *new_wire = it.second.new_wire;
 			if (new_wire->port_id > 0)
-				new_cell->connections()[new_wire->name] = RTLIL::SigSpec(old_wire);
+				new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire));
 		}
 	}
 

passes/memory/memory_dff.cc

@@ -52,10 +52,10 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 					continue;
 			}
 
-			RTLIL::SigSpec q_norm = cell->connections()[after ? "\\D" : "\\Q"];
+			RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q");
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections()[after ? "\\Q" : "\\D"]);
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D"));
 			if (d.size() != 1)
 				continue;
 
@@ -127,8 +127,11 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	for (auto &cell_it : module->cells) {
 		RTLIL::Cell *cell = cell_it.second;
-		if (cell->type == "$dff")
+		if (cell->type == "$dff") {
-			cell->get("\\Q").replace(sig, newsig);
+			RTLIL::SigSpec new_q = cell->get("\\Q");
+			new_q.replace(sig, newsig);
+			cell->set("\\Q", new_q);
+		}
 	}
 }
 

passes/memory/memory_share.cc

@@ -72,8 +72,11 @@ struct MemoryShareWorker
 
 		for (int i = 0; i < int(sig_s.size()); i++)
 			if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
-				if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions))
+				if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
-					cell->get("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+					RTLIL::SigSpec new_b = cell->get("\\B");
+					new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+					cell->set("\\B", new_b);
+				}
 				return false;
 			}
 				
@@ -86,16 +89,22 @@ struct MemoryShareWorker
 			std::map<RTLIL::SigBit, bool> new_state = state;
 			new_state[sig_s[i]] = true;
 
-			if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions))
+			if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
-				cell->get("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+				RTLIL::SigSpec new_b = cell->get("\\B");
+				new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+				cell->set("\\B", new_b);
+			}
 		}
 
 		std::map<RTLIL::SigBit, bool> new_state = state;
 		for (int i = 0; i < int(sig_s.size()); i++)
 			new_state[sig_s[i]] = false;
 
-		if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions))
+		if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
-			cell->get("\\A").replace(bit_idx, RTLIL::State::Sx);
+			RTLIL::SigSpec new_a = cell->get("\\A");
+			new_a.replace(bit_idx, RTLIL::State::Sx);
+			cell->set("\\A", new_a);
+		}
 
 		return false;
 	}
@@ -239,7 +248,7 @@ struct MemoryShareWorker
 
 			if (created_conditions) {
 				log("    Added enable logic for %d different cases.\n", created_conditions);
-				cell->get("\\EN") = cell_en;
+				cell->set("\\EN", cell_en);
 			}
 		}
 	}
@@ -399,7 +408,7 @@ struct MemoryShareWorker
 
 				// Force this ports addr input to addr directly (skip don't care muxes)
 
-				cell->get("\\ADDR") = addr;
+				cell->set("\\ADDR", addr);
 
 				// If any of the ports between `last_i' and `i' write to the same address, this
 				// will have priority over whatever `last_i` wrote. So we need to revisit those
@@ -443,8 +452,8 @@ struct MemoryShareWorker
 
 				// Connect the new EN and DATA signals and remove the old write port.
 
-				cell->get("\\EN") = merged_en;
+				cell->set("\\EN", merged_en);
-				cell->get("\\DATA") = merged_data;
+				cell->set("\\DATA", merged_data);
 
 				module->remove(wr_ports[last_i]);
 				wr_ports[last_i] = NULL;
@@ -595,8 +604,8 @@ struct MemoryShareWorker
 
 			RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
 
-			wr_ports[i]->get("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
+			wr_ports[i]->set("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
-			wr_ports[i]->get("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active);
+			wr_ports[i]->set("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
 
 			std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
 			RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
@@ -614,7 +623,7 @@ struct MemoryShareWorker
 			}
 
 			module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
-			wr_ports[i]->get("\\EN") = en;
+			wr_ports[i]->set("\\EN", en);
 
 			module->remove(wr_ports[i-1]);
 			wr_ports[i-1] = NULL;

passes/opt/opt_clean.cc

@@ -189,13 +189,13 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		}
 	}
 
-	module->connections().clear();
+	module->connections_.clear();
 
 	SigPool used_signals;
 	SigPool used_signals_nodrivers;
 	for (auto &it : module->cells) {
 		RTLIL::Cell *cell = it.second;
-		for (auto &it2 : cell->connections()) {
+		for (auto &it2 : cell->connections_) {
 			assign_map.apply(it2.second);
 			used_signals.add(it2.second);
 			if (!ct.cell_output(cell->type, it2.first))

passes/opt/opt_const.cc

@@ -73,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 
 static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
 {
-	RTLIL::SigSpec Y = cell->connections()[out_port];
+	RTLIL::SigSpec Y = cell->get(out_port);
 	out_val.extend_u0(Y.size(), false);
 
 	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
@@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover("opt.opt_const.fine.$reduce_and");
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->get("\\A") = sig_a = new_a;
+					cell->set("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->get("\\A") = sig_a = new_a;
+					cell->set("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
 					log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
-					cell->get("\\B") = sig_b = new_b;
+					cell->set("\\B", sig_b = new_b);
 					cell->parameters.at("\\B_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -441,8 +441,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				cover("opt.opt_const.mux_to_inv");
 				cell->type = "$_INV_";
 				cell->set("\\A", input.extract(0, 1));
-				cell->connections().erase("\\B");
+				cell->unset("\\B");
-				cell->connections().erase("\\S");
+				cell->unset("\\S");
 				goto next_cell;
 			}
 			if (input.match("11 ")) ACTION_DO_Y(1);
@@ -510,7 +510,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (a.is_fully_const()) {
 				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
-				std::swap(cell->get("\\A"), cell->get("\\B"));
+				RTLIL::SigSpec tmp = cell->get("\\A");
+				cell->set("\\A", cell->get("\\B"));
+				cell->set("\\B", tmp);
 			}
 
 			if (b.is_fully_const()) {
@@ -522,7 +524,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cell->type = "$not";
 					cell->parameters.erase("\\B_WIDTH");
 					cell->parameters.erase("\\B_SIGNED");
-					cell->connections().erase("\\B");
+					cell->unset("\\B");
 				}
 				goto next_cell;
 			}
@@ -585,13 +587,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
 
 				if (!identity_wrt_a) {
-					cell->get("\\A") = cell->get("\\B");
+					cell->set("\\A", cell->get("\\B"));
 					cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
 					cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
 				}
 
 				cell->type = identity_bu0 ? "$bu0" : "$pos";
-				cell->connections().erase("\\B");
+				cell->unset("\\B");
 				cell->parameters.erase("\\B_WIDTH");
 				cell->parameters.erase("\\B_SIGNED");
 				cell->check();
@@ -613,8 +615,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
 			cell->set("\\A", cell->get("\\S"));
-			cell->connections().erase("\\B");
+			cell->unset("\\B");
-			cell->connections().erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -631,7 +633,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
 			cell->set("\\A", cell->get("\\S"));
-			cell->connections().erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -650,7 +652,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
 			cell->set("\\B", cell->get("\\S"));
-			cell->connections().erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -701,9 +703,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 			if (cell->get("\\S").size() != new_s.size()) {
 				cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
-				cell->get("\\A") = new_a;
+				cell->set("\\A", new_a);
-				cell->get("\\B") = new_b;
+				cell->set("\\B", new_b);
-				cell->get("\\S") = new_s;
+				cell->set("\\S", new_s);
 				if (new_s.size() > 1) {
 					cell->type = "$pmux";
 					cell->parameters["\\S_WIDTH"] = new_s.size();

passes/opt/opt_reduce.cc

@@ -215,13 +215,19 @@ struct OptReduceWorker
 					log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
 
 			cell->set("\\A", RTLIL::SigSpec());
-			for (auto &in_tuple : consolidated_in_tuples)
+			for (auto &in_tuple : consolidated_in_tuples) {
-				cell->get("\\A").append(in_tuple.at(0));
+				RTLIL::SigSpec new_a = cell->get("\\A");
+				new_a.append(in_tuple.at(0));
+				cell->set("\\A", new_a);
+			}
 
 			cell->set("\\B", RTLIL::SigSpec());
 			for (int i = 1; i <= cell->get("\\S").size(); i++)
-				for (auto &in_tuple : consolidated_in_tuples)
+				for (auto &in_tuple : consolidated_in_tuples) {
-					cell->get("\\B").append(in_tuple.at(i));
+					RTLIL::SigSpec new_b = cell->get("\\B");
+					new_b.append(in_tuple.at(i));
+					cell->set("\\B", new_b);
+				}
 
 			cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
 			cell->set("\\Y", new_sig_y);

passes/opt/opt_share.cc

@@ -263,7 +263,7 @@ struct OptShareWorker
 					log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
 					for (auto &it : cell->connections()) {
 						if (ct.cell_output(cell->type, it.first)) {
-							RTLIL::SigSpec other_sig = sharemap[cell]->connections()[it.first];
+							RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first);
 							log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
 									log_signal(it.second), log_signal(other_sig));
 							module->connect(RTLIL::SigSig(it.second, other_sig));

passes/proc/proc_dff.cc

@@ -160,15 +160,15 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 
 	RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
 	mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_set->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
+	mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
-	mux_sr_set->connections()[set_polarity ? "\\B" : "\\A"] = sig_set;
+	mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set);
 	mux_sr_set->set("\\Y", sig_sr_set);
 	mux_sr_set->set("\\S", set);
 
 	RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
 	mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_clr->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
+	mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
-	mux_sr_clr->connections()[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
+	mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv);
 	mux_sr_clr->set("\\Y", sig_sr_clr);
 	mux_sr_clr->set("\\S", set);
 

passes/proc/proc_mux.cc

@@ -174,8 +174,15 @@ static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
 	assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
-	last_mux_cell->get("\\S").append(ctrl_sig);
+
-	last_mux_cell->get("\\B").append(when_signal);
+	RTLIL::SigSpec new_s = last_mux_cell->get("\\S");
+	new_s.append(ctrl_sig);
+	last_mux_cell->set("\\S", new_s);
+
+	RTLIL::SigSpec new_b = last_mux_cell->get("\\B");
+	new_b.append(when_signal);
+	last_mux_cell->set("\\B", new_b);
+
 	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size();
 }
 

passes/sat/expose.cc

@@ -485,12 +485,12 @@ struct ExposePass : public Pass {
 				for (auto &it : module->cells) {
 					if (!ct.cell_known(it.second->type))
 						continue;
-					for (auto &conn : it.second->connections())
+					for (auto &conn : it.second->connections_)
 						if (ct.cell_input(it.second->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}
 
-				for (auto &conn : module->connections())
+				for (auto &conn : module->connections_)
 					conn.second = out_to_in_map(sigmap(conn.second));
 			}
 
@@ -518,7 +518,7 @@ struct ExposePass : public Pass {
 					for (auto &bit : cell_q_bits)
 						if (wire_bits_set.count(bit))
 							bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
-					cell->get("\\Q") = cell_q_bits;
+					cell->set("\\Q", cell_q_bits);
 				}
 
 				RTLIL::Wire *wire_q = new RTLIL::Wire;

passes/sat/freduce.cc

@@ -708,7 +708,7 @@ struct FreduceWorker
 
 				RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
 				RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
-				for (auto &port : drv->connections())
+				for (auto &port : drv->connections_)
 					if (ct.cell_output(drv->type, port.first))
 						sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
 

passes/sat/miter.cc

@@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			w2->width = w1->width;
 			miter_module->add(w2);
 
-			gold_cell->connections()[w1->name] = w2;
+			gold_cell->set(w1->name, w2);
-			gate_cell->connections()[w1->name] = w2;
+			gate_cell->set(w1->name, w2);
 		}
 
 		if (w1->port_output)
@@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			w2_gate->width = w1->width;
 			miter_module->add(w2_gate);
 
-			gold_cell->connections()[w1->name] = w2_gold;
+			gold_cell->set(w1->name, w2_gold);
-			gate_cell->connections()[w1->name] = w2_gate;
+			gate_cell->set(w1->name, w2_gate);
 
 			RTLIL::SigSpec this_condition;
 

passes/sat/share.cc

@@ -258,7 +258,9 @@ struct ShareWorker
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
 				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					unsigned_cell->get("\\A").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					new_a.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				unsigned_cell->check();
@@ -312,7 +314,10 @@ struct ShareWorker
 
 				if (score_flipped < score_unflipped)
 				{
-					std::swap(c2->get("\\A"), c2->get("\\B"));
+					RTLIL::SigSpec tmp = c2->get("\\A");
+					c2->set("\\A", c2->get("\\B"));
+					c2->set("\\B", tmp);
+
 					std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
 					std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
 					modified_src_cells = true;
@@ -325,7 +330,9 @@ struct ShareWorker
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
 				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					unsigned_cell->get("\\A").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					new_a.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				modified_src_cells = true;
@@ -336,7 +343,9 @@ struct ShareWorker
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
 				if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
-					unsigned_cell->get("\\B").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_b = unsigned_cell->get("\\B");
+					new_b.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\B", new_b);
 				}
 				unsigned_cell->parameters.at("\\B_SIGNED") = true;
 				modified_src_cells = true;

passes/techmap/dfflibmap.cc

@@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 			} else
 			if (port.second != 0)
 				log_abort();
-			new_cell->connections()["\\" + port.first] = sig;
+			new_cell->set("\\" + port.first, sig);
 		}
 
 		stats[stringf("  mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;

passes/techmap/extract.cc

@@ -305,7 +305,7 @@ namespace
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
 					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
-				cell->connections()[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
+				cell->set(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
 			}
 		}
 
@@ -325,7 +325,9 @@ namespace
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
 						RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1);
-						cell->connections().at(port.first).replace(port.second, bitsig);
+						RTLIL::SigSpec new_sig = cell->get(port.first);
+						new_sig.replace(port.second, bitsig);
+						cell->set(port.first, new_sig);
 					}
 				}
 			}
@@ -744,7 +746,7 @@ struct ExtractPass : public Pass {
 						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires.at(chunk.wire->name);
-						newCell->connections()[conn.first] = chunks;
+						newCell->set(conn.first, chunks);
 					}
 				}
 			}

passes/techmap/hilomap.cc

@@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
-				cell->connections()[RTLIL::escape_id(hicell_portname)] = last_hi;
+				cell->set(RTLIL::escape_id(hicell_portname), last_hi);
 			}
 			bit = last_hi;
 		}
@@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
-				cell->connections()[RTLIL::escape_id(locell_portname)] = last_lo;
+				cell->set(RTLIL::escape_id(locell_portname), last_lo);
 			}
 			bit = last_lo;
 		}

passes/techmap/iopadmap.cc

@@ -177,9 +177,9 @@ struct IopadmapPass : public Pass {
 					for (int i = 0; i < wire->width; i++)
 					{
 						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-						cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
+						cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
 						if (!portname2.empty())
-							cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
+							cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())
@@ -190,9 +190,9 @@ struct IopadmapPass : public Pass {
 				else
 				{
 					RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-					cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
+					cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
 					if (!portname2.empty())
-						cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
+						cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
 					if (!widthparam.empty())
 						cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
 					if (!nameparam.empty())

passes/techmap/simplemap.cc

@@ -128,7 +128,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$reduce_bool") gate_type = "$_OR_";
 	log_assert(!gate_type.empty());
 
-	RTLIL::SigSpec *last_output = NULL;
+	RTLIL::Cell *last_output_cell = NULL;
 
 	while (sig_a.size() > 1)
 	{
@@ -145,7 +145,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 			gate->set("\\A", sig_a[i]);
 			gate->set("\\B", sig_a[i+1]);
 			gate->set("\\Y", sig_t[i/2]);
-			last_output = &gate->get("\\Y");
+			last_output_cell = gate;
 		}
 
 		sig_a = sig_t;
@@ -156,14 +156,14 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
 		gate->set("\\A", sig_a);
 		gate->set("\\Y", sig_t);
-		last_output = &gate->get("\\Y");
+		last_output_cell = gate;
 		sig_a = sig_t;
 	}
 
-	if (last_output == NULL) {
+	if (last_output_cell == NULL) {
 		module->connect(RTLIL::SigSig(sig_y, sig_a));
 	} else {
-		*last_output = sig_y;
+		last_output_cell->set("\\Y", sig_y);
 	}
 }
 

passes/techmap/techmap.cc

@@ -195,7 +195,7 @@ struct TechmapWorker
 			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
 				c->type = c->type.substr(1);
 
-			for (auto &it2 : c->connections()) {
+			for (auto &it2 : c->connections_) {
 				apply_prefix(cell->name, it2.second, module);
 				port_signal_map.apply(it2.second);
 			}