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add wide luts

This commit is contained in:
Pepijn de Vos 2019-10-28 12:49:08 +01:00
parent 5fad53b504
commit f88335a8a5
3 changed files with 119 additions and 36 deletions
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24
techlibs/gowin/cells_map.v
View File

@ -101,6 +101,30 @@ module \$lut (A, Y);
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else
if (WIDTH == 5) begin
wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1));
MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else
if (WIDTH == 6) begin
wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1));
MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1));
MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1));
MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end

35
techlibs/gowin/cells_sim.v
View File

@ -24,6 +24,41 @@ module LUT4(output F, input I0, I1, I2, I3);
assign F = I0 ? s1[1] : s1[0];
endmodule
module MUX2 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
assign O = S0 ? I1 : I0;
endmodule
module MUX2_LUT5 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
MUX2 mux2_lut5 (O, I0, I1, S0);
endmodule
module MUX2_LUT6 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
MUX2 mux2_lut6 (O, I0, I1, S0);
endmodule
module MUX2_LUT7 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
MUX2 mux2_lut7 (O, I0, I1, S0);
endmodule
module MUX2_LUT8 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
MUX2 mux2_lut8 (O, I0, I1, S0);
endmodule
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;

26
techlibs/gowin/synth_gowin.cc
View File

@ -64,6 +64,12 @@ struct SynthGowinPass : public ScriptPass
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
log(" -nowidelut\n");
log(" do not use muxes to implement LUTs larger than LUT4s\n");
log("\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@ -71,7 +77,7 @@ struct SynthGowinPass : public ScriptPass
}
string top_opt, vout_file;
bool retime, nobram, nodram, flatten, nodffe;
bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9;
void clear_flags() YS_OVERRIDE
{
@ -82,6 +88,8 @@ struct SynthGowinPass : public ScriptPass
nobram = false;
nodffe = false;
nodram = false;
nowidelut = false;
abc9 = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -128,6 +136,14 @@ struct SynthGowinPass : public ScriptPass
flatten = false;
continue;
}
if (args[argidx] == "-nowidelut") {
nowidelut = true;
continue;
}
if (args[argidx] == "-abc9") {
abc9 = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -203,7 +219,15 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts"))
{
if (nowidelut && abc9) {
run("abc9 -lut 4");
} else if (nowidelut && !abc9) {
run("abc -lut 4");
} else if (!nowidelut && abc9) {
run("abc9 -lut 4:8");
} else if (!nowidelut && !abc9) {
run("abc -lut 4:8");
}
run("clean");
}