mirror of https://github.com/YosysHQ/yosys.git
abc9 to write_aiger with -O option, and ignore dummy outputs
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@ -412,8 +412,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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handle_loops(design, module);
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handle_loops(design, module);
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Pass::call(design, "write_verilog -norename -noexpr input.v");
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Pass::call(design, "write_verilog -norename -noexpr input.v");
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Pass::call(design, stringf("write_xaiger -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
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Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
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Pass::call(design, stringf("write_xaiger -ascii -symbols %s/input.xaag; read_aiger -wideports -map %s/input.symbols %s/input.xaag; write_verilog -norename -noexpr input.v", tempdir_name.c_str(), tempdir_name.c_str(), tempdir_name.c_str()));
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Pass::call(design, stringf("write_xaiger -ascii -symbols %s/input.xaag; read_aiger -wideports %s/input.xaag; write_verilog -norename -noexpr input.v", tempdir_name.c_str(), tempdir_name.c_str()));
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// Now 'unexpose' those wires by undoing
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// Now 'unexpose' those wires by undoing
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// the expose operation -- remove them from PO/PI
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// the expose operation -- remove them from PO/PI
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@ -547,6 +547,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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output_bits.insert({wire, i});
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output_bits.insert({wire, i});
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}
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}
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else {
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else {
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if (w->name.str() == "\\__dummy_o__") {
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log("Don't call ABC as there is nothing to map.\n");
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goto cleanup;
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}
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auto r = wideports_split(w->name.str());
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auto r = wideports_split(w->name.str());
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wire = module->wire(r.first);
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wire = module->wire(r.first);
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log_assert(wire);
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log_assert(wire);
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@ -875,6 +880,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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Pass::call(design, "clean");
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Pass::call(design, "clean");
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cleanup:
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if (cleanup)
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if (cleanup)
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{
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{
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log("Removing temp directory.\n");
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log("Removing temp directory.\n");
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