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mark DSPs as TODOs for now

This commit is contained in:
Miodrag Milanovic 2024-03-13 10:07:54 +01:00
parent 8f42d6dace
commit f836de6bcc
3 changed files with 198 additions and 197 deletions
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195
techlibs/nanoxplore/cells_bb.v
View File

@ -1,50 +1,3 @@
(* blackbox *)
module ACC84_2DSP(clk, rst, X, Z);
input [83:0] X;
output [84:0] Z;
input clk;
input rst;
parameter g_pipe = 2;
endmodule
(* blackbox *)
module ACC92_2DSP(clk, rst, X, Z);
input [55:0] X;
output [91:0] Z;
input clk;
input rst;
parameter g_pipe = 2;
endmodule
(* blackbox *)
module ACC98_2DSP(clk, rst, X, Z);
input [55:0] X;
output [97:0] Z;
input clk;
input rst;
parameter g_pipe = 2;
endmodule
(* blackbox *)
module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z);
input [41:0] X;
input [41:0] Y;
output [84:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module ADD84_2DSP(clk, rst, X, Y, Z);
input [83:0] X;
input [83:0] Y;
output [84:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *) (* blackbox *)
module NX_BD(I, O); module NX_BD(I, O);
input I; input I;
@ -3242,151 +3195,3 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD
parameter turbo = ""; parameter turbo = "";
parameter weakTermination = ""; parameter weakTermination = "";
endmodule endmodule
(* blackbox *)
module SMACC24x18_1DSP(clk, rst, A, B, Z);
input [23:0] A;
input [17:0] B;
output [55:0] Z;
input clk;
input rst;
parameter g_pipe = 1;
endmodule
(* blackbox *)
module SMACC24x32_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [31:0] B;
output [55:0] Z;
input clk;
input rst;
parameter g_pipe = 1;
endmodule
(* blackbox *)
module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z);
input [23:0] A;
input [31:0] B;
output [55:0] Z;
input clk;
input rst;
input we;
parameter STAGE_1 = "false";
parameter STAGE_2 = "false";
parameter STAGE_3 = "false";
parameter STAGE_4 = "false";
endmodule
(* blackbox *)
module SMUL24x32_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [31:0] B;
output [54:0] Z;
input clk;
input rst;
parameter g_pipe = 1;
endmodule
(* blackbox *)
module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z);
input [23:0] A;
input [31:0] B;
output [97:0] Z;
input clk;
input rst;
input we;
parameter STAGE_1 = "false";
parameter STAGE_2 = "false";
parameter STAGE_3 = "false";
endmodule
(* blackbox *)
module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
input [23:0] A;
input [31:0] B;
output [91:0] Z;
input clk;
input rst;
input we;
endmodule
(* blackbox *)
module SMUL47x35_4DSP(clk, rst, A, B, Z);
input [46:0] A;
input [34:0] B;
output [80:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module UMADD24_2DSP(clk, rst, A, B, C, Z);
input [23:0] A;
input [31:0] B;
input [55:0] C;
output [55:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z);
input [23:0] A;
input [15:0] B;
output [55:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module UMUL24x32_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [31:0] B;
output [55:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z);
input [23:0] A;
input [17:0] B;
output [59:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module UMUL24x36_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [35:0] B;
output [59:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z);
input [23:0] A;
input [17:0] B;
output [83:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
(* blackbox *)
module UMUL48x36_4DSP(clk, rst, A, B, Z);
input [47:0] A;
input [35:0] B;
output [83:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule

11
techlibs/nanoxplore/cells_wrap_l.v
View File

@ -1400,3 +1400,14 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
.WE(WE) .WE(WE)
); );
endmodule endmodule
// TODO
module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
input [23:0] A;
input [31:0] B;
output [91:0] Z;
input clk;
input rst;
input we;
endmodule

185
techlibs/nanoxplore/cells_wrap_u.v
View File

@ -2519,3 +2519,188 @@ module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO,
.REQ1(REQ) .REQ1(REQ)
); );
endmodule endmodule
//TODO
module ACC84_2DSP(clk, rst, X, Z);
input [83:0] X;
output [84:0] Z;
input clk;
input rst;
parameter g_pipe = 2;
endmodule
//TODO
module ACC92_2DSP(clk, rst, X, Z);
input [55:0] X;
output [91:0] Z;
input clk;
input rst;
parameter g_pipe = 2;
endmodule
//TODO
module ACC98_2DSP(clk, rst, X, Z);
input [55:0] X;
output [97:0] Z;
input clk;
input rst;
parameter g_pipe = 2;
endmodule
//TODO
module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z);
input [41:0] X;
input [41:0] Y;
output [84:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module ADD84_2DSP(clk, rst, X, Y, Z);
input [83:0] X;
input [83:0] Y;
output [84:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module SMACC24x18_1DSP(clk, rst, A, B, Z);
input [23:0] A;
input [17:0] B;
output [55:0] Z;
input clk;
input rst;
parameter g_pipe = 1;
endmodule
//TODO
module SMACC24x32_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [31:0] B;
output [55:0] Z;
input clk;
input rst;
parameter g_pipe = 1;
endmodule
//TODO
module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z);
input [23:0] A;
input [31:0] B;
output [55:0] Z;
input clk;
input rst;
input we;
parameter STAGE_1 = "false";
parameter STAGE_2 = "false";
parameter STAGE_3 = "false";
parameter STAGE_4 = "false";
endmodule
//TODO
module SMUL24x32_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [31:0] B;
output [54:0] Z;
input clk;
input rst;
parameter g_pipe = 1;
endmodule
//TODO
module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z);
input [23:0] A;
input [31:0] B;
output [97:0] Z;
input clk;
input rst;
input we;
parameter STAGE_1 = "false";
parameter STAGE_2 = "false";
parameter STAGE_3 = "false";
endmodule
//TODO
module SMUL47x35_4DSP(clk, rst, A, B, Z);
input [46:0] A;
input [34:0] B;
output [80:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module UMADD24_2DSP(clk, rst, A, B, C, Z);
input [23:0] A;
input [31:0] B;
input [55:0] C;
output [55:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z);
input [23:0] A;
input [15:0] B;
output [55:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module UMUL24x32_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [31:0] B;
output [55:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z);
input [23:0] A;
input [17:0] B;
output [59:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module UMUL24x36_2DSP(clk, rst, A, B, Z);
input [23:0] A;
input [35:0] B;
output [59:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z);
input [23:0] A;
input [17:0] B;
output [83:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule
//TODO
module UMUL48x36_4DSP(clk, rst, A, B, Z);
input [47:0] A;
input [35:0] B;
output [83:0] Z;
input clk;
input rst;
parameter piped = "true";
endmodule