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Update `gate_cost_equivalent` help

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Martin Povišer 2024-12-03 11:09:15 +01:00
parent 69a36aec3b
commit f81dbf2433
1 changed files with 5 additions and 4 deletions
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@ -354,6 +354,11 @@ Verilog Attributes and non-standard features
- The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten`` - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
command from flattening the indicated cells and modules. command from flattening the indicated cells and modules.
- The `gate_cost_equivalent` attribute on a module can be used to specify
the estimated cost of the module as a number of basic gate instances. See
the help message of command `keep_hierarchy` which interprets this
attribute.
- The ``init`` attribute on wires is set by the frontend when a register is - The ``init`` attribute on wires is set by the frontend when a register is
initialized "FPGA-style" with ``reg foo = val``. It can be used during initialized "FPGA-style" with ``reg foo = val``. It can be used during
synthesis to add the necessary reset logic. synthesis to add the necessary reset logic.
@ -575,10 +580,6 @@ Non-standard or SystemVerilog features for formal verification
``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>`` ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
is marked with the ``(* gclk *)`` Verilog attribute. is marked with the ``(* gclk *)`` Verilog attribute.
- The `gate_cost_equivalent` attribute on a module can be used to specify
the estimated cost of a module as an equivalent number of basic gate
instances.
Supported features from SystemVerilog Supported features from SystemVerilog
===================================== =====================================