From cb285e4b87112779efe84a7b6c5ae4a76a69ae01 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 May 2019 15:33:47 +0200 Subject: [PATCH 1/7] Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 Signed-off-by: Clifford Wolf --- passes/pmgen/peepopt_shiftmul.pmg | 15 +++++++++++---- tests/simple/peepopt.v | 4 ++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index fe861b728..6adab4e5f 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -1,4 +1,7 @@ pattern shiftmul +// +// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] +// state shamt @@ -49,12 +52,16 @@ code if (GetSize(port(shift, \Y)) > const_factor) reject; + int factor_bits = ceil_log2(const_factor); + SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A); + + if (GetSize(shamt) < factor_bits+GetSize(mul_din)) + reject; + did_something = true; log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); - int new_const_factor_log2 = ceil_log2(const_factor); - int new_const_factor = 1 << new_const_factor_log2; - + int new_const_factor = 1 << factor_bits; SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec old_a = port(shift, \A), new_a; int trunc = 0; @@ -73,7 +80,7 @@ code if (trunc > 0) new_a.remove(GetSize(new_a)-trunc, trunc); - SigSpec new_b = {port(mul, const_factor_port == \A ? \B : \A), SigSpec(State::S0, new_const_factor_log2)}; + SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; if (param(shift, \B_SIGNED).as_bool()) new_b.append(State::S0); diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v index b27b9fe57..1bf427897 100644 --- a/tests/simple/peepopt.v +++ b/tests/simple/peepopt.v @@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in assign o = i[s*W+:W]; endmodule +module peepopt_shiftmul_1 (output y, input [2:0] w); +assign y = 1'b1 >> (w * (3'b110)); +endmodule + module peepopt_muldiv_0(input [1:0] i, output [1:0] o); wire [3:0] t; assign t = i * 3; From 14bd40cd3d760e22eeaf6f9622e210412e2b93a6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 29 May 2019 18:57:03 +0200 Subject: [PATCH 2/7] Aded one more load of .conf to support change of prefix --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index 05b28f33d..76dac48a5 100644 --- a/Makefile +++ b/Makefile @@ -46,6 +46,10 @@ OS := $(shell uname -s) PREFIX ?= /usr/local INSTALL_SUDO := +ifneq ($(wildcard Makefile.conf),) +include Makefile.conf +endif + BINDIR := $(PREFIX)/bin LIBDIR := $(PREFIX)/lib DATDIR := $(PREFIX)/share/yosys From 2faa1d0e80d213461d4403e36499aaaf1c8088b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 30 May 2019 10:03:54 +0200 Subject: [PATCH 3/7] Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055 Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 21a1bbbbe..33d2ac7a8 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2016,6 +2016,9 @@ struct VerificPass : public Pass { // WARNING: instantiating unknown module 'XYZ' (VERI-1063) Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + // https://github.com/YosysHQ/yosys/issues/1055 + RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; + #ifndef DB_PRESERVE_INITIAL_VALUE # warning Verific was built without DB_PRESERVE_INITIAL_VALUE. #endif From 90ec2cda4217115fb91206a712befb3e6fa797e5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 31 May 2019 09:28:51 +0200 Subject: [PATCH 4/7] Fix "tee" handling of log_streams Signed-off-by: Clifford Wolf --- passes/cmds/tee.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index ee96ace86..1a44bdaec 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -52,7 +52,9 @@ struct TeePass : public Pass { void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector backup_log_files, files_to_close; + std::vector backup_log_streams; int backup_log_verbose_level = log_verbose_level; + backup_log_streams = log_streams; backup_log_files = log_files; size_t argidx; @@ -60,6 +62,7 @@ struct TeePass : public Pass { { if (args[argidx] == "-q" && files_to_close.empty()) { log_files.clear(); + log_streams.clear(); continue; } if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) { @@ -89,6 +92,7 @@ struct TeePass : public Pass { for (auto cf : files_to_close) fclose(cf); log_files = backup_log_files; + log_streams = backup_log_streams; throw; } @@ -97,6 +101,7 @@ struct TeePass : public Pass { log_verbose_level = backup_log_verbose_level; log_files = backup_log_files; + log_streams = backup_log_streams; } } TeePass; From 36120fcc3064d0be20d5b9871a804b226471ceae Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 2 Jun 2019 10:14:50 +0200 Subject: [PATCH 5/7] Only support Symbiotic EDA flavored Verific Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 33d2ac7a8..2bf99e58e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -48,6 +48,14 @@ USING_YOSYS_NAMESPACE #include "VhdlUnits.h" #include "VeriLibrary.h" +#ifndef SYMBIOTIC_VERIFIC_API_VERSION +# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific." +#endif + +#if SYMBIOTIC_VERIFIC_API_VERSION < 1 +# error "Please update your version of Symbiotic EDA flavored Verific." +#endif + #ifdef __clang__ #pragma clang diagnostic pop #endif From 0ad50332d94dfd4e08dcb8e862ccdd91b4262eb2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 19:36:09 -0700 Subject: [PATCH 6/7] Execute techmap and arith_map simultaneously --- techlibs/xilinx/synth_xilinx.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c20cac09b..a569c20f4 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -229,11 +229,6 @@ struct SynthXilinxPass : public ScriptPass run("dff2dffe"); run("opt -full"); - if (!vpr || help_mode) - run("techmap -map +/xilinx/arith_map.v"); - else - run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, // so break those down here @@ -242,7 +237,12 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } - run("techmap"); + if (!vpr || help_mode) + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + else + run("techmap -map +/techmap.v +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + + run("opt -fast"); } From 02973474df5b0b88b1744baa9cec703d089ff007 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 20:04:47 -0700 Subject: [PATCH 7/7] Remove extra newline --- techlibs/xilinx/synth_xilinx.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a569c20f4..a293081f1 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -242,7 +242,6 @@ struct SynthXilinxPass : public ScriptPass else run("techmap -map +/techmap.v +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - run("opt -fast"); }