mirror of https://github.com/YosysHQ/yosys.git
SigSpec refactoring: added RTLIL::SigSpec::operator[]
This commit is contained in:
parent
e7e30f1c86
commit
f80da7b41d
|
@ -522,6 +522,9 @@ public:
|
||||||
|
|
||||||
int size() const { return width_; }
|
int size() const { return width_; }
|
||||||
|
|
||||||
|
RTLIL::SigBit &operator[](int index) { unpack(); return bits_.at(index); }
|
||||||
|
const RTLIL::SigBit &operator[](int index) const { unpack(); return bits_.at(index); }
|
||||||
|
|
||||||
void expand();
|
void expand();
|
||||||
void optimize();
|
void optimize();
|
||||||
RTLIL::SigSpec optimized() const;
|
RTLIL::SigSpec optimized() const;
|
||||||
|
@ -540,7 +543,7 @@ public:
|
||||||
void remove_const();
|
void remove_const();
|
||||||
|
|
||||||
RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const;
|
RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const;
|
||||||
RTLIL::SigSpec extract(int offset, int length) const;
|
RTLIL::SigSpec extract(int offset, int length = 1) const;
|
||||||
|
|
||||||
void append(const RTLIL::SigSpec &signal);
|
void append(const RTLIL::SigSpec &signal);
|
||||||
void append_bit(const RTLIL::SigBit &bit);
|
void append_bit(const RTLIL::SigBit &bit);
|
||||||
|
|
Loading…
Reference in New Issue