diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 1bc0cc688..2d42c23ad 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -1,7 +1,9 @@
 #!/bin/bash
 set -ex
 sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
-cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+if [ ! -f "test_dsp_model_ref.v" ]; then
+	cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+fi
 for tb in testbench \
 		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
 		testbench_seq_16x16_A testbench_seq_16x16_B