riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

read_aiger to only clean own design

This commit is contained in:
Eddie Hung 2019-05-28 08:45:10 -07:00
parent 4a76b425cc
commit f745727de5
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
frontends/aiger/aigerparse.cc
View File

@ -722,8 +722,14 @@ void AigerReader::post_process()
module->fixup_ports(); module->fixup_ports();
design->add(module); design->add(module);
design->selection_stack.emplace_back(false);
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
Pass::call(design, "clean"); Pass::call(design, "clean");
design->selection_stack.pop_back();
for (auto cell : module->cells().to_vector()) { for (auto cell : module->cells().to_vector()) {
if (cell->type != "$lut") continue; if (cell->type != "$lut") continue;
auto y_port = cell->getPort("\\Y").as_bit(); auto y_port = cell->getPort("\\Y").as_bit();