mirror of https://github.com/YosysHQ/yosys.git
Add builtin celltype $scopeinfo
Only declares the cell interface, doesn't make anything use or understand $scopeinfo yet.
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@ -108,6 +108,7 @@ struct CellTypes
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setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
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setup_type(ID($original_tag), {ID::A}, {ID::Y});
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setup_type(ID($future_ff), {ID::A}, {ID::Y});
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setup_type(ID($scopeinfo), {}, {});
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}
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void setup_internals_eval()
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@ -1769,6 +1769,15 @@ namespace {
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return;
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}
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if (cell->type == ID($scopeinfo)) {
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param(ID::TYPE);
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check_expected();
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std::string scope_type = cell->getParam(ID::TYPE).decode_string();
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if (scope_type != "module" && scope_type != "struct")
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error(__LINE__);
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return;
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}
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if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
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if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
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if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
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@ -1379,6 +1379,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
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return true;
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}
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if (cell->type == ID($scopeinfo))
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{
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return true;
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}
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// Unsupported internal cell types: $pow $fsm $mem*
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// .. and all sequential cells with asynchronous inputs
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return false;
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@ -2763,3 +2763,10 @@ assign Y = A;
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endmodule
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// --------------------------------------------------------
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(* noblackbox *)
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module \$scopeinfo ();
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parameter TYPE = "";
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endmodule
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