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Update CHANGELOG

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Eddie Hung 2019-04-08 16:22:07 -07:00
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commit f6c354c55b
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@ -16,7 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "gate2lut.v" techmap rule - Added "gate2lut.v" techmap rule
- Added "rename -src" - Added "rename -src"
- Added "equiv_opt" pass - Added "equiv_opt" pass
- Added "shregmap -tech xilinx", used by "synth_xilinx" - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
Yosys 0.7 .. Yosys 0.8 Yosys 0.7 .. Yosys 0.8