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Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.

This commit is contained in:
Alberto Gonzalez 2020-04-01 05:25:10 +00:00
parent 68c0e3562e
commit f657fed24c
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GPG Key ID: 8395A8BA109708B2
1 changed files with 19 additions and 22 deletions
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41
backends/verilog/verilog_backend.cc
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@ -73,12 +73,12 @@ void reset_auto_counter(RTLIL::Module *module)
reset_auto_counter_id(module->name, false); reset_auto_counter_id(module->name, false);
for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) for (auto w : module->wires())
reset_auto_counter_id(it->second->name, true); reset_auto_counter_id(w->name, true);
for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) { for (auto cell : module->cells()) {
reset_auto_counter_id(it->second->name, true); reset_auto_counter_id(cell->name, true);
reset_auto_counter_id(it->second->type, false); reset_auto_counter_id(cell->type, false);
} }
for (auto it = module->processes.begin(); it != module->processes.end(); ++it) for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
@ -1719,9 +1719,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
if (!noexpr) if (!noexpr)
{ {
std::set<std::pair<RTLIL::Wire*,int>> reg_bits; std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
for (auto &it : module->cells_) for (auto cell : module->cells())
{ {
RTLIL::Cell *cell = it.second;
if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q")) if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q"))
continue; continue;
@ -1734,9 +1733,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i)); reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i));
} }
} }
for (auto &it : module->wires_) for (auto wire : module->wires())
{ {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++) for (int i = 0; i < wire->width; i++)
if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0) if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
goto this_wire_aint_reg; goto this_wire_aint_reg;
@ -1751,8 +1749,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
bool keep_running = true; bool keep_running = true;
for (int port_id = 1; keep_running; port_id++) { for (int port_id = 1; keep_running; port_id++) {
keep_running = false; keep_running = false;
for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) { for (auto wire : module->wires()) {
RTLIL::Wire *wire = it->second;
if (wire->port_id == port_id) { if (wire->port_id == port_id) {
if (port_id != 1) if (port_id != 1)
f << stringf(", "); f << stringf(", ");
@ -1764,14 +1761,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
} }
f << stringf(");\n"); f << stringf(");\n");
for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) for (auto w : module->wires())
dump_wire(f, indent + " ", it->second); dump_wire(f, indent + " ", w);
for (auto it = module->memories.begin(); it != module->memories.end(); ++it) for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
dump_memory(f, indent + " ", it->second); dump_memory(f, indent + " ", it->second);
for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) for (auto cell : module->cells())
dump_cell(f, indent + " ", it->second); dump_cell(f, indent + " ", cell);
for (auto it = module->processes.begin(); it != module->processes.end(); ++it) for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
dump_process(f, indent + " ", it->second); dump_process(f, indent + " ", it->second);
@ -1995,16 +1992,16 @@ struct VerilogBackend : public Backend {
design->sort(); design->sort();
*f << stringf("/* Generated by %s */\n", yosys_version_str); *f << stringf("/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { for (auto module : design->modules()) {
if (it->second->get_blackbox_attribute() != blackboxes) if (module->get_blackbox_attribute() != blackboxes)
continue; continue;
if (selected && !design->selected_whole_module(it->first)) { if (selected && !design->selected_whole_module(module->name)) {
if (design->selected_module(it->first)) if (design->selected_module(module->name))
log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first)); log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
continue; continue;
} }
log("Dumping module `%s'.\n", it->first.c_str()); log("Dumping module `%s'.\n", module->name.c_str());
dump_module(*f, "", it->second); dump_module(*f, "", module);
} }
auto_name_map.clear(); auto_name_map.clear();