mirror of https://github.com/YosysHQ/yosys.git
booth: Drop extra decoder arguments
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579f6bdc17
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@ -337,9 +337,7 @@ struct BoothPassWorker {
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BuildBoothUMultDecoderRowN(module,
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X, // multiplicand
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one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i,
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false, // include sign
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false // include constant
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one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i
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);
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// data, shift, sign
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ppij_int.push_back(std::make_tuple(ppij_row_n, i * 2, s_int[i]));
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@ -413,7 +411,7 @@ struct BoothPassWorker {
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void BuildBoothUMultDecoderRowN(RTLIL::Module *module,
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SigSpec X, // multiplicand
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SigSpec one_int, SigSpec two_int, SigSpec s_int, SigSpec sb_int,
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SigSpec &ppij_vec, int row_ix, bool no_sign, bool no_constant)
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SigSpec &ppij_vec, int row_ix)
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{
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(void)module;
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int x_sz = GetSize(X);
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@ -430,12 +428,10 @@ struct BoothPassWorker {
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ppij_vec.append(Bur4d_msb("row_dec_red", X[x_sz - 1], two_int, s_int));
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// sign bit
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if (!no_sign) // if no sign is false then make a sign bit
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ppij_vec.append(sb_int);
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ppij_vec.append(sb_int);
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// constant bit
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if (!no_constant) // if non constant is false make a constant bit
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ppij_vec.append(State::S1);
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ppij_vec.append(State::S1);
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}
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void DebugDumpAlignPP(std::vector<std::vector<RTLIL::Wire *>> &aligned_pp)
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