mirror of https://github.com/YosysHQ/yosys.git
genrtlil: Fix displaying debug info in packages
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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@ -1126,8 +1126,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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// everything should have been handled above -> print error if not.
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default:
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AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod;
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for (auto f : log_files)
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current_ast_mod->dumpAst(f, "verilog-ast> ");
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current_scope_ast->dumpAst(f, "verilog-ast> ");
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log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
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}
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