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support file locations containing spaces

This commit is contained in:
Miodrag Milanovic 2022-08-08 20:30:50 +02:00
parent 6c65ca4e50
commit f4a1906721
6 changed files with 19 additions and 18 deletions
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2
passes/sat/qbfsat.cc
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@ -216,7 +216,7 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt,
QbfSolutionType ret; QbfSolutionType ret;
const std::string yosys_smtbmc_exe = proc_self_dirname() + "yosys-smtbmc"; const std::string yosys_smtbmc_exe = proc_self_dirname() + "yosys-smtbmc";
const std::string smtbmc_warning = "z3: WARNING:"; const std::string smtbmc_warning = "z3: WARNING:";
const std::string smtbmc_cmd = stringf("%s -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1", const std::string smtbmc_cmd = stringf("\"%s\" -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1",
yosys_smtbmc_exe.c_str(), opt.get_solver_name().c_str(), yosys_smtbmc_exe.c_str(), opt.get_solver_name().c_str(),
(opt.timeout != 0? stringf("--timeout %d", opt.timeout) : "").c_str(), (opt.timeout != 0? stringf("--timeout %d", opt.timeout) : "").c_str(),
(opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file : "").c_str(), (opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file : "").c_str(),

10
passes/techmap/abc.cc
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@ -789,15 +789,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str()); std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str());
if (!liberty_files.empty() || !genlib_files.empty()) { if (!liberty_files.empty() || !genlib_files.empty()) {
for (std::string liberty_file : liberty_files) for (std::string liberty_file : liberty_files)
abc_script += stringf("read_lib -w %s; ", liberty_file.c_str()); abc_script += stringf("read_lib -w \"%s\"; ", liberty_file.c_str());
for (std::string liberty_file : genlib_files) for (std::string liberty_file : genlib_files)
abc_script += stringf("read_library %s; ", liberty_file.c_str()); abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str());
if (!constr_file.empty()) if (!constr_file.empty())
abc_script += stringf("read_constr -v %s; ", constr_file.c_str()); abc_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str());
} else } else
if (!lut_costs.empty()) if (!lut_costs.empty())
abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
@ -1085,7 +1085,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
fclose(f); fclose(f);
} }
buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str()); buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str()); log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
#ifndef YOSYS_LINK_ABC #ifndef YOSYS_LINK_ABC

6
passes/techmap/abc9_exe.cc
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@ -175,12 +175,12 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
if (!lut_costs.empty()) if (!lut_costs.empty())
abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
else if (!lut_file.empty()) else if (!lut_file.empty())
abc9_script += stringf("read_lut %s; ", lut_file.c_str()); abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str());
else else
log_abort(); log_abort();
log_assert(!box_file.empty()); log_assert(!box_file.empty());
abc9_script += stringf("read_box %s; ", box_file.c_str()); abc9_script += stringf("read_box \"%s\"; ", box_file.c_str());
abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str()); abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
if (!script_file.empty()) { if (!script_file.empty()) {
@ -264,7 +264,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
fclose(f); fclose(f);
} }
buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str()); buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str()); log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
#ifndef YOSYS_LINK_ABC #ifndef YOSYS_LINK_ABC

1
tests/arch/ice40/.gitignore vendored
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@ -1,4 +1,5 @@
*.log *.log
*.json
/run-test.mk /run-test.mk
+*_synth.v +*_synth.v
+*_testbench +*_testbench

2
tests/gen-tests-makefile.sh
View File

@ -17,7 +17,7 @@ generate_target() {
generate_ys_test() { generate_ys_test() {
ys_file=$1 ys_file=$1
yosys_args=${2:-} yosys_args=${2:-}
generate_target "$ys_file" "$YOSYS_BASEDIR/yosys -ql ${ys_file%.*}.log $yosys_args $ys_file" generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args $ys_file"
} }
# $ generate_bash_test bash_file # $ generate_bash_test bash_file

16
tests/tools/autotest.sh
View File

@ -1,6 +1,6 @@
#!/usr/bin/env bash #!/usr/bin/env bash
libs="" libs=()
genvcd=false genvcd=false
use_xsim=false use_xsim=false
use_modelsim=false use_modelsim=false
@ -15,7 +15,7 @@ xinclude_opts=""
minclude_opts="" minclude_opts=""
scriptfiles="" scriptfiles=""
scriptopt="" scriptopt=""
toolsdir="$(cd $(dirname $0); pwd)" toolsdir="$(cd "$(dirname "$0")"; pwd)"
warn_iverilog_git=false warn_iverilog_git=false
# The following are used in verilog to firrtl regression tests. # The following are used in verilog to firrtl regression tests.
# Typically these will be passed as environment variables: # Typically these will be passed as environment variables:
@ -25,8 +25,8 @@ firrtl2verilog=""
xfirrtl="../xfirrtl" xfirrtl="../xfirrtl"
abcprog="$toolsdir/../../yosys-abc" abcprog="$toolsdir/../../yosys-abc"
if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then
( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 ( set -ex; ${CC:-gcc} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1
fi fi
while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
@ -38,7 +38,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
G) G)
warn_iverilog_git=true ;; warn_iverilog_git=true ;;
l) l)
libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";; libs+=("$(cd "$(dirname "$OPTARG")"; pwd)/$(basename "$OPTARG")");;
w) w)
genvcd=true ;; genvcd=true ;;
k) k)
@ -162,7 +162,7 @@ do
cp ../${bn}_tb.v ${bn}_tb.v cp ../${bn}_tb.v ${bn}_tb.v
fi fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} $libs \ compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \
"$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v "$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
@ -171,11 +171,11 @@ do
test_passes() { test_passes() {
"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
${bn}_tb.v ${bn}_syn${test_count}.v $libs \ ${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
"$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v "$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count} "$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count}
test_count=$(( test_count + 1 )) test_count=$(( test_count + 1 ))
} }