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Add more tests

This commit is contained in:
Eddie Hung 2019-09-11 13:22:41 -07:00
parent bbef0d2ac8
commit f46ef47893
1 changed files with 32 additions and 0 deletions
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32
tests/various/peepopt.ys
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@ -78,3 +78,35 @@ clean
select -assert-count 1 t:$dff r:WIDTH=2 %i
select -assert-count 1 t:$mux r:WIDTH=2 %i
select -assert-count 0 t:$dff t:$mux %% t:* %D
###################
design -reset
read_verilog <<EOT
module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
endmodule
EOT
proc
equiv_opt -assert peepopt
design -load postopt
select -assert-count 1 t:$dff r:WIDTH=2 %i
select -assert-count 1 t:$mux r:WIDTH=2 %i
select -assert-count 0 t:$dff t:$mux %% t:* %D
###################
design -reset
read_verilog <<EOT
module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
endmodule
EOT
proc
equiv_opt -assert peepopt
design -load postopt
select -assert-count 1 t:$dff r:WIDTH=5 %i
select -assert-count 1 t:$mux r:WIDTH=5 %i
select -assert-count 0 t:$dff t:$mux %% t:* %D