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Add more tests
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@ -78,3 +78,35 @@ clean
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=5 %i
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select -assert-count 1 t:$mux r:WIDTH=5 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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