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Merge pull request #2273 from whitequark/write-verilog-always-star-initial 

verilog_backend: in non-SV mode, add a trigger for `always @*`
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clairexen 2020-07-16 18:30:50 +02:00 committed by GitHub
parent c49344b262 128522f173
commit f3d7e9a1df
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1 changed files with 5 additions and 0 deletions
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5
backends/verilog/verilog_backend.cc
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@ -1718,6 +1718,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
} }
f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*"); f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*");
if (!systemverilog)
f << indent + " " << "if (" << id("\\initial") << ") begin end\n";
dump_case_body(f, indent, &proc->root_case, true); dump_case_body(f, indent, &proc->root_case, true);
std::string backup_indent = indent; std::string backup_indent = indent;
@ -1850,6 +1852,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
} }
f << stringf(");\n"); f << stringf(");\n");
if (!systemverilog && !module->processes.empty())
f << indent + " " << "reg " << id("\\initial") << " = 0;\n";
for (auto w : module->wires()) for (auto w : module->wires())
dump_wire(f, indent + " ", w); dump_wire(f, indent + " ", w);