mirror of https://github.com/YosysHQ/yosys.git
Added help messages to memory_* passes
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@ -23,7 +23,22 @@
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#include <stdio.h>
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#include <stdio.h>
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struct MemoryPass : public Pass {
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struct MemoryPass : public Pass {
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MemoryPass() : Pass("memory") { }
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MemoryPass() : Pass("memory", "translate memories to basic cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory [selection]\n");
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log("\n");
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log("This pass calls all the other memory_* passes in a useful order:\n");
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log("\n");
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log(" memory_dff\n");
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log(" memory_collect\n");
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log(" memory_map\n");
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log("\n");
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log("This converts memories to word-wide DFFs and address decoders.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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log_header("Executing MEMORY pass.\n");
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log_header("Executing MEMORY pass.\n");
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@ -161,22 +161,38 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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module->cells[mem->name] = mem;
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module->cells[mem->name] = mem;
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}
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}
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static void handle_module(RTLIL::Module *module)
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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{
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for (auto &mem_it : module->memories) {
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std::vector<RTLIL::IdString> delme;
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handle_memory(module, mem_it.second);
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for (auto &mem_it : module->memories)
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delete mem_it.second;
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if (design->selected(module, mem_it.second)) {
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handle_memory(module, mem_it.second);
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delme.push_back(mem_it.first);
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}
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for (auto &it : delme) {
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delete module->memories.at(it);
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module->memories.erase(it);
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}
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}
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module->memories.clear();
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}
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}
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struct MemoryCollectPass : public Pass {
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struct MemoryCollectPass : public Pass {
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MemoryCollectPass() : Pass("memory_collect") { }
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MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_collect [selection]\n");
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log("\n");
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log("This pass collects memories and memory ports and creates generic multiport\n");
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log("memory cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
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log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
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extra_args(args, 1, design);
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules)
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handle_module(mod_it.second);
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second);
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}
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}
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} MemoryCollectPass;
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} MemoryCollectPass;
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@ -178,9 +178,11 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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}
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#endif
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#endif
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static void handle_module(RTLIL::Module *module)
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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{
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for (auto &cell_it : module->cells) {
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for (auto &cell_it : module->cells) {
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if (!design->selected(module, cell_it.second))
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continue;
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if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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handle_wr_cell(module, cell_it.second);
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handle_wr_cell(module, cell_it.second);
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if (cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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if (cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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@ -189,12 +191,24 @@ static void handle_module(RTLIL::Module *module)
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}
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}
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struct MemoryDffPass : public Pass {
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struct MemoryDffPass : public Pass {
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MemoryDffPass() : Pass("memory_dff") { }
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MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_dff [selection]\n");
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log("\n");
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log("This pass detects DFFs at memory ports and merges them into the memory port.\n");
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log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
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log("interface and yields a synchronous memory port.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
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log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
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extra_args(args, 1, design);
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules)
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handle_module(mod_it.second);
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second);
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}
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}
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} MemoryDffPass;
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} MemoryDffPass;
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@ -312,23 +312,34 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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return;
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return;
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}
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}
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static void handle_module(RTLIL::Module *module)
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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{
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std::vector<RTLIL::Cell*> cells;
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std::vector<RTLIL::Cell*> cells;
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for (auto &it : module->cells)
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for (auto &it : module->cells)
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if (it.second->type == "$mem")
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if (it.second->type == "$mem" && design->selected(module, it.second))
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cells.push_back(it.second);
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cells.push_back(it.second);
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for (auto cell : cells)
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for (auto cell : cells)
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handle_cell(module, cell);
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handle_cell(module, cell);
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}
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}
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struct MemoryMapPass : public Pass {
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struct MemoryMapPass : public Pass {
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MemoryMapPass() : Pass("memory_map") { }
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MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_map [selection]\n");
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log("\n");
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log("This pass converts multiport memory cells as generated by the memory_collect\n");
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log("pass to word-wide DFFs and address decoders.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
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log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
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extra_args(args, 1, design);
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules)
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handle_module(mod_it.second);
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second);
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}
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}
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} MemoryMapPass;
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} MemoryMapPass;
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