mirror of https://github.com/YosysHQ/yosys.git
Cleanups in igloo2 example design
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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# Add placement constraints here
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# Add timing constraints here
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read_verilog example.v
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synth_sf2 -top example -edif netlist.edn
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write_verilog netlist.vm
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@ -14,14 +14,12 @@ new_project \
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import_files -hdl_source {netlist.vm}
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import_files -hdl_source {netlist.vm}
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import_files -sdc {example.sdc}
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import_files -sdc {example.sdc}
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import_files -io_pdc {example.io.pdc}
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import_files -io_pdc {example.pdc}
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import_files -fp_pdc {example.fp.pdc}
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set_option -synth 0
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set_option -synth 0
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organize_tool_files -tool PLACEROUTE \
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organize_tool_files -tool PLACEROUTE \
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-file {proj/constraint/example.sdc} \
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-file {proj/constraint/example.sdc} \
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-file {proj/constraint/io/example.io.pdc} \
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-file {proj/constraint/io/example.pdc} \
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-file {proj/constraint/fp/example.fp.pdc} \
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-input_type constraint
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-input_type constraint
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organize_tool_files -tool VERIFYTIMING \
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organize_tool_files -tool VERIFYTIMING \
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