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ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map 

The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2019-07-16 23:57:15 +02:00
parent 5939b5d636
commit f28e38de99
2 changed files with 4 additions and 4 deletions
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6
techlibs/ice40/ice40_unlut.cc
View File

@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module)
cell->unsetParam("\\LUT_INIT");
cell->setPort("\\A", SigSpec({
get_bit_or_zero(cell->getPort("\\I3")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I0")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I0"))
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I3"))
}));
cell->setPort("\\Y", cell->getPort("\\O")[0]);
cell->unsetPort("\\I0");

2
techlibs/ice40/synth_ice40.cc
View File

@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass
}
run("clean");
run("ice40_unlut");
run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
}
if (check_label("map_cells"))