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log_debug() for abc9_{arrival,required} times

This commit is contained in:
Eddie Hung 2020-01-10 17:13:27 -08:00
parent 28f814ee59
commit f24de88f38
2 changed files with 15 additions and 1 deletions
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8
backends/aiger/xaiger.cc
View File

@ -254,6 +254,14 @@ struct XAigerWriter
log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
auto jt = arrivals.begin(); auto jt = arrivals.begin();
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
}
#endif
for (auto bit : sigmap(conn.second)) { for (auto bit : sigmap(conn.second)) {
arrival_times[bit] = *jt; arrival_times[bit] = *jt;
if (arrivals.size() > 1) if (arrivals.size() > 1)

8
passes/techmap/abc9_ops.cc
View File

@ -512,7 +512,7 @@ void prep_times(RTLIL::Design *design)
requireds.clear(); requireds.clear();
for (auto cell : boxes) { for (auto cell : boxes) {
RTLIL::Module* inst_module = module->design->module(cell->type); RTLIL::Module* inst_module = module->design->module(cell->type);
log_assert(inst_module);
for (auto &conn : cell->connections_) { for (auto &conn : cell->connections_) {
auto port_wire = inst_module->wire(conn.first); auto port_wire = inst_module->wire(conn.first);
if (!port_wire->port_input) if (!port_wire->port_input)
@ -537,6 +537,12 @@ void prep_times(RTLIL::Design *design)
SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
for (const auto &i : requireds) { for (const auto &i : requireds) {
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), i.first);
}
#endif
delays.insert(i.first); delays.insert(i.first);
for (auto offset : i.second) { for (auto offset : i.second) {
auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY)); auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));