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Fix INIT for variable length SRs that have been bumped up one

This commit is contained in:
Eddie Hung 2019-03-19 14:54:43 -07:00
parent 24553326dd
commit f239cb821e
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/cells_map.v
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@ -106,7 +106,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
else begin else begin
// For variable length, bump up to the next length // For variable length, bump up to the next length
// because we can't access Q31 // because we can't access Q31
\$__SHREG_ #(.DEPTH(DEPTH+1), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q)); \$__SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
end end
end end
else begin else begin