mirror of https://github.com/YosysHQ/yosys.git
Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
This commit is contained in:
parent
6294621825
commit
f235f212ea
|
@ -490,8 +490,8 @@ struct TechmapWorker
|
||||||
}
|
}
|
||||||
|
|
||||||
TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
|
TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
|
||||||
dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
|
dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
|
||||||
dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
|
dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
|
||||||
|
|
||||||
for (auto cell : module->selected_cells())
|
for (auto cell : module->selected_cells())
|
||||||
{
|
{
|
||||||
|
|
Loading…
Reference in New Issue