From 0787af947f92d9d1040623b5d2e8c737c0aee0a9 Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Thu, 9 Apr 2020 05:34:28 +0000
Subject: [PATCH 1/3] Clean up `passes/cmds/scatter.cc`.

---
 passes/cmds/scatter.cc | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 7123ba9fb..8c95e4289 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -46,22 +46,19 @@ struct ScatterPass : public Pass {
 		CellTypes ct(design);
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules_)
+		for (auto module : design->selected_modules())
 		{
-			if (!design->selected(mod_it.second))
-				continue;
-
-			for (auto &c : mod_it.second->cells_)
-			for (auto &p : c.second->connections_)
+			for (auto cell : module->cells())
+			for (auto &p : cell->connections_)
 			{
-				RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
+				RTLIL::Wire *wire = module->addWire(NEW_ID, p.second.size());
 
-				if (ct.cell_output(c.second->type, p.first)) {
+				if (ct.cell_output(cell->type, p.first)) {
 					RTLIL::SigSig sigsig(p.second, wire);
-					mod_it.second->connect(sigsig);
+					module->connect(sigsig);
 				} else {
 					RTLIL::SigSig sigsig(wire, p.second);
-					mod_it.second->connect(sigsig);
+					module->connect(sigsig);
 				}
 
 				p.second = wire;

From 0424555702de0c17841d8306f734faa788bc504d Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Thu, 9 Apr 2020 23:55:24 +0000
Subject: [PATCH 2/3] Replace pseudo-private member access to `connections_` in
 `passes/cmds/scatter.cc`.

Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
---
 passes/cmds/scatter.cc | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 8c95e4289..cd1b3286f 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -48,20 +48,17 @@ struct ScatterPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
-			for (auto cell : module->cells())
-			for (auto &p : cell->connections_)
-			{
-				RTLIL::Wire *wire = module->addWire(NEW_ID, p.second.size());
-
-				if (ct.cell_output(cell->type, p.first)) {
-					RTLIL::SigSig sigsig(p.second, wire);
-					module->connect(sigsig);
-				} else {
-					RTLIL::SigSig sigsig(wire, p.second);
-					module->connect(sigsig);
+			for (auto cell : module->cells()) {
+				std::map<RTLIL::IdString, std::pair<RTLIL::SigSpec, RTLIL::SigSpec>> new_connections;
+				for (auto conn : cell->connections())
+					new_connections.emplace(conn.first, std::make_pair(conn.second, module->addWire(NEW_ID, conn.second.size())));
+				for (auto &it : new_connections) {
+					if (ct.cell_output(cell->type, it.first))
+						module->connect(RTLIL::SigSig(it.second.first, it.second.second));
+					else
+						module->connect(RTLIL::SigSig(it.second.second, it.second.first));
+					cell->setPort(it.first, it.second.second);
 				}
-
-				p.second = wire;
 			}
 		}
 	}

From ff8be2364e9d9aecb084f7fff07a2538b5e6d02e Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Mon, 13 Apr 2020 19:37:01 +0000
Subject: [PATCH 3/3] Replace `std::map` with `dict`.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
---
 passes/cmds/scatter.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index cd1b3286f..a5ef95f02 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -49,9 +49,9 @@ struct ScatterPass : public Pass {
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->cells()) {
-				std::map<RTLIL::IdString, std::pair<RTLIL::SigSpec, RTLIL::SigSpec>> new_connections;
+				dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
 				for (auto conn : cell->connections())
-					new_connections.emplace(conn.first, std::make_pair(conn.second, module->addWire(NEW_ID, conn.second.size())));
+					new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
 				for (auto &it : new_connections) {
 					if (ct.cell_output(cell->type, it.first))
 						module->connect(RTLIL::SigSig(it.second.first, it.second.second));