mirror of https://github.com/YosysHQ/yosys.git
Fixed simlib.v model for $mem
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5867f6bcdc
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@ -1346,13 +1346,13 @@ generate
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always @(WR_ADDR or WR_DATA or WR_EN) begin
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run_update = 0;
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for (n = 0; n < WIDTH; n = n+1) begin
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if (WR_EN[i][n]) begin
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if (WR_EN[i*WIDTH + n]) begin
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found_collision = 0;
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for (k = i+1; k < WR_PORTS; k = k+1)
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if (WR_EN[k][n] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ])
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if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
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found_collision = 1;
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if (!found_collision) begin
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data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ][n] <= WR_DATA[ i*WIDTH +: WIDTH ][n];
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data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
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run_update = 1;
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end
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end
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@ -1367,13 +1367,13 @@ generate
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always @(posedge WR_CLK[i]) begin
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run_update = 0;
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for (n = 0; n < WIDTH; n = n+1) begin
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if (WR_EN[i][n]) begin
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if (WR_EN[i*WIDTH + n]) begin
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found_collision = 0;
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for (k = i+1; k < WR_PORTS; k = k+1)
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if (WR_EN[k][n] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ])
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if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
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found_collision = 1;
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if (!found_collision) begin
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data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ][n] <= WR_DATA[ i*WIDTH +: WIDTH ][n];
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data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
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run_update = 1;
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end
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end
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@ -1387,13 +1387,13 @@ generate
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always @(negedge WR_CLK[i]) begin
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run_update = 0;
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for (n = 0; n < WIDTH; n = n+1) begin
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if (WR_EN[i][n]) begin
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if (WR_EN[i*WIDTH + n]) begin
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found_collision = 0;
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for (k = i+1; k < WR_PORTS; k = k+1)
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if (WR_EN[k][n] && WR_ADDR[ i*ABITS +: ABITS ] == WR_ADDR[ k*ABITS +: ABITS ])
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if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
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found_collision = 1;
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if (!found_collision) begin
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data[ WR_ADDR[ i*ABITS +: ABITS ] - OFFSET ][n] <= WR_DATA[ i*WIDTH +: WIDTH ][n];
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data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
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run_update = 1;
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end
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end
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